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參數(shù)資料
| 型號(hào)： | GS8170DW36C-250 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁(yè)數(shù)： | 5/27頁(yè) |
| 文件大?。?/td> | 827K |
| 代理商： | GS8170DW36C-250 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)
GS8170DW36/72C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.04 5/2005
5/27
2002, GSI Technology, Inc.
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins
Single Data Rate (SDR) Pipelined Read.
Read A
Deselect
Read B
Read C
Read D
A
B
C
D
E
Q(A)
Q(B)
Q(C)
Q(D)
CK
Address
ADV
E1
W
DQ
CQ
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8170DW36C-250I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36C-300 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36C-333 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36C-333I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW72C-200 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8170DW36C-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW72AC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays |
| GS8170DW72AC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays |
| GS8170DW72AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays |
| GS8170DW72AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays |
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