參數(shù)資料
型號: GS8162V72CGC-300
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 256K x 72 18Mb S/DCD Sync Burst SRAMs
中文描述: 256K X 72 CACHE SRAM, 5 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁數(shù): 5/29頁
文件大?。?/td> 675K
代理商: GS8162V72CGC-300
GS8162V72CC-333/300/250/200/150
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 2/2005
5/29
2004, GSI Technology
Mode Pin Functions
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Power Down Control
ZZ
L or NC
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關PDF資料
PDF描述
GS8162V72CGC-30I 256K x 72 18Mb S/DCD Sync Burst SRAMs
GS8162V72CGC-333 256K x 72 18Mb S/DCD Sync Burst SRAMs
GS8162V72CGC-333I 256K x 72 18Mb S/DCD Sync Burst SRAMs
GS8162Z72CC 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z72CC-150 18Mb Pipelined and Flow Through Synchronous NBT SRAM
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