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參數(shù)資料
| 型號： | GS816272CC-150V |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 256K X 72 CACHE SRAM, 7.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 851K |
| 代理商： | GS816272CC-150V |
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First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
3.
GS816272CC-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 6/2006
9/29
2004, GSI Technology
Simplified State Diagram with G
相關PDF資料 |
PDF描述 |
|---|---|
| GS816272CC-200IV | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
| GS816272CC-200V | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
| GS816272CC-250IV | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
| GS816272CC-250V | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
| GS816272CC-V | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS816272CC-200 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 6.5NS/3NS 209FBGA - Trays |
| GS816272CC-200I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 6.5NS/3NS 209FBGA - Trays |
| GS816272CC-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 6.5NS/3NS 209FBGA - Trays |
| GS816272CC-200M | 制造商:GSI Technology 功能描述:2.5 OR 3.3V - Trays |
| GS816272CC-200V | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 6.5NS/3NS 209FBGA - Trays |
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