參數(shù)資料
型號： GS816218B-250
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
中文描述： 1M X 18 CACHE SRAM, 5.5 ns, PBGA119
封裝： FBGA-119
文件頁數(shù)： 31/41頁
文件大小： 980K
代理商： GS816218B-250
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GS816218(B/D)/GS816236(B/D)/GS816272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.17 11/2004
31/41
1999, GSI Technology
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
1
BYPASS
111
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
相關(guān)PDF資料
PDF描述
GS816218B-250I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-133 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-133I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-150 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-150I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS816218BB-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FBGA - Trays
GS816218BB-150I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FBGA - Trays
GS816218BB-150IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FPBGA - Trays
GS816218BB-150V 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FPBGA - Trays
GS816218BB-200 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 6.5NS/3NS 119FBGA - Trays
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