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參數(shù)資料
| 型號： | GS8161Z18D-166T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-LFBGA 0 to 70 |
| 中文描述： | 35.7流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 939K |
| 代理商： | GS8161Z18D-166T |
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GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
4/36
1998, GSI Technology
100-Pin TQFP Pin Descriptions
Symbol
Type
Description
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
Clock Input Signal
B
A
In
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
B
B
In
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
B
C
In
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
B
D
In
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
W
In
Write Enable; active low
E
1
In
Chip Enable; active low
E
2
In
Chip Enable—Active High. For self decoded depth expansion
E
3
In
Chip Enable—Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
NC
—
No Connect
DQ
A
I/O
Byte A Data Input and Output pins
DQ
B
I/O
Byte B Data Input and Output pins
DQ
C
I/O
Byte C Data Input and Output pins
DQ
D
I/O
Byte D Data Input and Output pins
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
ZZ
In
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
LBO
In
Linear Burst Order; active low.
V
DD
In
Core power supply
V
SS
In
Ground
V
DDQ
In
Output driver power supply
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|---|---|
| GS8161Z18D-200 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200IT | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200T | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-225 | Enhanced Product 26-Bit Registered Buffer With Sstl_2 Inputs And Lvcmos Outputs 96-LFBGA -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161Z18D-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200IT | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200T | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-225 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
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