參數(shù)資料
型號: GS8161Z18
廠商: Electronic Theatre Controls, Inc.
英文描述: 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 64-TSSOP 0 to 70
中文描述: 35.7流水線和流量,通過同步唑的SRAM
文件頁數(shù): 12/36頁
文件大?。?/td> 939K
代理商: GS8161Z18
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
12/36
1998, GSI Technology
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+2)
Transition
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate
State
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline Mode Data I/O State Diagram
Next State
相關(guān)PDF資料
PDF描述
GS8161Z18D-166 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
GS8161Z18D-166I 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
GS8161Z18D-166IT 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-BGA MICROSTAR 0 to 70
GS8161Z18D-166T 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-LFBGA 0 to 70
GS8161Z18D-200 18Mb Pipelined and Flow Through Synchronous NBT SRAM
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