參數(shù)資料
型號(hào)： GS8161E3T-200
廠商： Electronic Theatre Controls, Inc.
英文描述： 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
中文描述： 100萬(wàn)× 18，512k × 32的，為512k × 36 35.7同步突發(fā)靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 35/36頁(yè)
文件大?。?/td> 939K
代理商： GS8161E3T-200
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
35/36
1998, GSI Technology
18Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
GS18/36 1.00 9/
1999A;GS18/362.0012/
1999B
Content
Converted from 0.25u 3.3V process to 0.18u 2.5V process.
Master File Rev B
Added x72 Pinout.
GS18/362.00 12/
1999BGS18/362.01 1/2000C
Format
Added new GSI Logo
GS18/362.0 1/2000DGS18/
362.03 2/2000E
Front page; Features - changed 2.5V I/O supply to 2.5V
or3.3V I/O supply; Completeness
Absolute Maximum Ratings; Changed VDDQ - Value: From: -
.05 to VDD : to : -.05 to 3.6; Completeness.
Recommended Operating Conditions;Changed: I/O Supply
Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from
VDD +0.3 to 3.6; Same page - took out Note 1;Completeness
Electrical Characteristics - Added second Output High Voltage
line to table; completeness.
Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
Pin 14 removed from V
SS
in pin description table.
ADV changed to pin 85 in pin description table.
GS18/362.03 2/2000E;
8161Z18_r2_04
Content
8161Z18_r2_04;
8161Z18_r2_05
Content
Changed the value of ZZ recovery in the AC Electrical Char-
acteristics table on page 18 from 20 ns to 100 ns
8161Z18_r2_05;
8161Z18_r2_06
Content/Format
Added 225 MHz speed bin
Updated page 1 table, AC Characteristics table, and Operat-
ing Currents table
Updated format to comply with Technical Publications stan-
dards
Updated Capitance table—removed Input row and updated
Output row to I/O
Updated Features list on page 1
Completely reworked table on page 1
Updated Mode Pin Functions on page 12
Added 3.3 V references to entire document
Updated Operating Conditions table
Updated JTAG Operating Conditions table
Updated Boundary Scan Chain table
Updated Opearting Currents table and added note
Updated table on page 1; added power numbers
Updated Pin Description table
Updated DQ on page 21
Updated DQ on page 23
Updated Operating Currrents table
Updated table on page 1; updated power numbers
Updated Recommended Operating Conditions table (added
V
DDQ
references)
8161Z18_r2_06;
8161Z18_r2_07
Content
8161Z18_r2_07;
8161Z18_r2_08
Content
8161Z18_r2_08;
8161Z18_r2_09
Content
相關(guān)PDF資料
PDF描述
GS8161Z18 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 64-TSSOP 0 to 70
GS8161Z18D-166 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
GS8161Z18D-166I 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
GS8161Z18D-166IT 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-BGA MICROSTAR 0 to 70
GS8161Z18D-166T 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-LFBGA 0 to 70
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