參數(shù)資料
型號(hào)： GS816136D-225
廠商： Electronic Theatre Controls, Inc.
英文描述： Pin Strip Header; No. of Contacts:36; Pitch Spacing:0.1"; No. of Rows:2; Contact Material:Copper Alloy; Contact Plating:Gold; Leaded Process Compatible:Yes; Mounting Type:PCB Straight Thru Hole; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes
中文描述： 165焊球BGA封裝？x18 Commom的I / O？頂視圖（D組）
文件頁(yè)數(shù)： 32/40頁(yè)
文件大?。?/td> 1391K
代理商： GS816136D-225
Rev: 2.12 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
24/32
1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
0
1
1
Bit #
x36
x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
· · ·
· · ·
n
0
1
2
0
1
2
· · ·
0
1
2
· · ·
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
相關(guān)PDF資料
PDF描述
GS816136D-225I 165 Bump BGA?x18 Commom I/O?Top View (Package D)
GS816136D-250 Pin Strip Header; No. of Contacts:36; Pitch Spacing:0.1"; No. of Rows:2; Contact Material:Copper Alloy; Contact Plating:Gold; Mounting Type:PCB Straight Thru Hole; Terminal Type:Solder Tail; Pin Length:0.318" RoHS Compliant: Yes
GS816136D-250I .1" PIN STRIP HEADER
GS816136T-166I 165 Bump BGA?x18 Commom I/O?Top View (Package D)
GS816136 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS816136D-225I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D)
GS816136D-250 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D)
GS816136D-250I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D)
GS816136DD-150 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS816136DD-150I 制造商:GSI Technology 功能描述:165 BGA - Bulk
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