參數(shù)資料
型號: GS8160Z18
廠商: GSI TECHNOLOGY
英文描述: 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
中文描述: 16Mb的流水線和流量,通過同步唑的SRAM(1,600位流水線式和流通型同步唑靜態(tài)內(nèi)存)
文件頁數(shù): 12/24頁
文件大?。?/td> 476K
代理商: GS8160Z18
Rev: 2.08 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
12/24
1998, Giga Semiconductor, Inc.
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS8161Z18/36
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V
DD
or V
DDQ
on pipelined parts and V
SS
on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe parity
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode
applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By
using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT
SRAMs (GS8161Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active
low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
CK
ZZ
tZZR
tZZH
tZZS
~
~
Sleep
相關(guān)PDF資料
PDF描述
GS8160Z36 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
GS816118D-133 Pin Strip Header; No. of Contacts:36; Pitch Spacing:0.1"; No. of Rows:2; Contact Material:Copper Alloy; Contact Plating:Gold; Leaded Process Compatible:Yes; Mounting Type:PCB Straight Thru Hole; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes
GS816118D-133I 165 Bump BGA?x18 Commom I/O?Top View (Package D)
GS816118D-150 Pin Strip Header; No. of Contacts:36; Pitch Spacing:0.1"; No. of Rows:2; Contact Material:Copper Alloy; Contact Plating:Gold; Leaded Process Compatible:Yes; Mounting Type:PCB Straight Thru Hole; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes
GS816118D-150I 165 Bump BGA?x18 Commom I/O?Top View (Package D)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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GS8160Z18BGT-150I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Trays
GS8160Z18BGT-150IT 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8160Z18BGT-150IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Trays
GS8160Z18BGT-150T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM