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參數(shù)資料
| 型號： | GS8152Z72 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM) |
| 中文描述： | 16Mb的流水線和流量，通過同步唑的SRAM（1,600位流水線式和流通型同步唑靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 8/39頁 |
| 文件大?。?/td> | 757K |
| 代理商： | GS8152Z72 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
8/39
2000, Giga Semiconductor, Inc.
Preliminary
GS8152Z18/36/72B-225/200/180/166/150/133
BPR1999.05.18
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
U3
U5
U4
TDI
TDO
TCK
V
DD
I
Scan Test Data In
Scan Test Data Out
Scan Test Clock
O
I
J2, C4, J4, R4, J6
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
A1, F1, J1, M1, U1, A7, F7,
J7, M7, U7
K4
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
CK
I
Clock Input Signal; active high
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
GS8152Z18/36 Pin Description
Pin Location
Symbol
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS816018 | 16Mb（1M x 18Bit）Sync Burst SRAM(16M位（1M x 18位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS816032 | 16Mb（512K x 36Bit）Sync Burst SRAM(16M位（512K x 36位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS816036 | 16Mb（256K x 72Bit）Sync Burst SRAM(16M位（256K x 72位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS816036T-133 | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS816036T-133I | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS815V018AB-250 | 制造商:GSI Technology 功能描述:GS815V018AB-250 - Trays |
| GS815V018AB-250I | 制造商:GSI Technology 功能描述:GS815V018AB-250I - Trays |
| GS815V018AB-300 | 制造商:GSI Technology 功能描述:GS815V018AB-300 - Trays |
| GS815V018AB-300I | 制造商:GSI Technology 功能描述:GS815V018AB-300I - Trays |
| GS815V018AB-333 | 制造商:GSI Technology 功能描述:GS815V018AB-333 - Trays |
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