參數(shù)資料
型號(hào): GS8152Z18
廠商: GSI TECHNOLOGY
英文描述: 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
中文描述: 16Mb的流水線和流量,通過同步唑的SRAM(1,600位流水線式和流通型同步唑靜態(tài)內(nèi)存)
文件頁數(shù): 29/39頁
文件大?。?/td> 757K
代理商: GS8152Z18
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
29/39
2000, Giga Semiconductor, Inc.
Preliminary
GS8152Z18/36/72B-225/200/180/166/150/133
ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed
ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1 compliant because some of the mandatory
instructions are uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads, but cannot be used to load
address, data or control signals into the RAM or to preload the I/O buffers.This device will not perform INTEST or the preload portion of the
SAMPLE / PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the
controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially
loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions
only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x32
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
x16
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
1
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