參數資料
型號： GS815236
廠商： GSI TECHNOLOGY
英文描述： 16Mb（512K x 36Bit）S/DCD Sync Burst SRAM(16M位（512K x 36位）可選單/雙循環(huán)取消同步靜態(tài)RAM（帶2位脈沖地址計數器）)
中文描述： 16Mb的（為512k × 36Bit）的S /雙氰胺同步突發(fā)靜態(tài)存儲器（1,600位（為512k × 36位）可選單/雙循環(huán)取消同步靜態(tài)隨機存儲器（帶2位脈沖地址計數器））
文件頁數： 31/38頁
文件大?。?/td> 824K
代理商： GS815236
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
31/38
2000, Giga Semiconductor, Inc.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Parameter
Symbol
V
IHT
V
ILT
I
INTH
I
INTL
I
OLT
V
OHT
V
OLT
Min.
0.7 * V
DD
Max.
V
DD
+0.3
0.3 * V
DD
Unit Notes
Test Port Input High Voltage
V
1, 2
Test Port Input Low Voltage
–
0.3
V
1, 2
TMS, TCK and TDI Input Leakage Current
–
300
1
uA
3
TMS, TCK and TDI Input Leakage Current
–
1
1
uA
4
TDO Output Leakage Current
–
1
1
uA
5
Test Port Output High Voltage
1.7
—
V
6, 7
Test Port Output Low Voltage
—
0.4
V
6, 8
Note:
1.
2.
3.
4.
5.
6.
7.
8.
This device features input buffers compatible with 2.5 V I/O drivers.
Input Under/overshoot voltage must be
–
2 V > Vi < V
DD
+2 V with a pulse width not to exceed 20% tTKC.
V
DD
≥
V
IN
≥
V
IL
0 V
≤
V
IN
≤
V
IL
Output Disable, V
OUT
= 0 to V
DD
The TDO output driver is served by the V
DD
supply.
I
OH
=
–
4 mA
I
OL
= + 4 mA
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as as shown unless otherwise noted.
Parameter
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Conditions
2.3 V
0.2 V
1 V/ns
1.25 V
1.25 V
DQ
V
T
= 1.25 V
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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