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參數(shù)資料
| 型號(hào)： | GS815236 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（512K x 36Bit）S/DCD Sync Burst SRAM(16M位（512K x 36位）可選單/雙循環(huán)取消同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 16Mb的（為512k × 36Bit）的S /雙氰胺同步突發(fā)靜態(tài)存儲(chǔ)器（1,600位（為512k × 36位）可選單/雙循環(huán)取消同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁(yè)數(shù)： | 13/38頁(yè) |
| 文件大小： | 824K |
| 代理商： | GS815236 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
13/38
2000, Giga Semiconductor, Inc.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
3.
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