參數(shù)資料
型號: GS74116AX-12T
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 256K x 16 4Mb Asynchronous SRAM
中文描述: 256K × 16 4Mb的異步SRAM
文件頁數(shù): 6/14頁
文件大?。?/td> 433K
代理商: GS74116AX-12T
Rev: 1.03 10/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6/14
2001, Giga Semiconductor, Inc.
GS74116ATP/J/X
AC Characteristics
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V
IL
, WE = V
IH
, UB and, or LB = V
IL
Read Cycle
Parameter
Symbol
-7
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
7
8
10
12
ns
Address access time
t
AA
7
8
10
12
ns
Chip enable access time (CE)
t
AC
7
8
10
12
ns
Byte enable access time (UB, LB)
t
AB
3
3.5
4
5
ns
Output enable to output valid (OE)
t
OE
3
3.5
4
5
ns
Output hold from address change
t
OH
3
3
3
3
ns
Chip enable to output in low Z (CE)
t
LZ
*
3
3
3
3
ns
Output enable to output in low Z (OE)
t
OLZ
*
0
0
0
0
ns
Byte enable to output in low Z (UB, LB)
t
BLZ
*
0
0
0
0
ns
Chip disable to output in High Z (CE)
t
HZ
*
3.5
4
5
6
ns
Output disable to output in High Z (OE)
t
OHZ
*
3
3.5
4
5
ns
Byte disable to output in High Z (UB, LB)
t
BHZ
*
3
3.5
4
5
ns
t
AA
t
OH
t
RC
Address
Data Out
Previous Data
Data valid
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