參數(shù)資料
型號(hào)： GS1561*
英文描述： Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply.
中文描述： 時(shí)鐘重計(jì)解串器的HD - SDI的。標(biāo)清SDI
文件頁數(shù)： 3/55頁
文件大?。?/td> 922K
GENNUM CORPORATION
27360 - 2
3 of 55
G
TABLE OF CONTENTS
1. PIN OUT ..........................................................................................................................................5
1.1 PIN ASSIGNMENT................................................................................................................5
1.2 PIN DESCRIPTIONS..............................................................................................................6
2. ELECTRICAL CHARACTERISTICS ........................................................................................................15
2.1 ABSOLUTE MAXIUMUM RATINGS........................................................................................15
2.2 DC ELECTRICAL CHARACTERISTICS......................................................................................16
2.3 AC ELECTRICAL CHARACTERISTICS......................................................................................17
2.4 INPUT/OUTPUT CIRCUITS ..................................................................................................19
2.5 HOST INTERFACE MAP.......................................................................................................20
3. DETAILED DESCRIPTION...................................................................................................................23
3.1 FUNCTIONAL OVERVIEW ....................................................................................................23
3.2 SERIAL DIGITAL INPUT .......................................................................................................23
3.2.1 INPUT SIGNAL SELECTION ................................................................................................................................23
3.2.2 CARRIER DETECT INPUT....................................................................................................................................23
3.2.3 SINGLE INPUT CONFIGURATION ......................................................................................................................23
3.3 SERIAL DIGITAL RECLOCKER ...............................................................................................23
3.3.1 EXTERNAL VCO...................................................................................................................................................24
3.3.2 LOOP BANDWIDTH.............................................................................................................................................24
3.4 SERIAL DIGITAL LOOP-THROUGH OUTPUT.............................................................................24
3.4.1 OUTPUT SWING..................................................................................................................................................24
3.4.2 RECLOCKER BYPASS CONTROL.......................................................................................................................24
3.4.3 SERIAL DIGITAL OUTPUT MUTE ........................................................................................................................24
3.5 SERIAL-TO-PARALLEL CONVERSION......................................................................................25
3.6 MODES OF OPERATION ......................................................................................................25
3.6.1 LOCK DETECT.....................................................................................................................................................25
3.6.2 MASTER MODE ...................................................................................................................................................26
3.6.3 SLAVE MODE.......................................................................................................................................................26
3.7 SMPTE FUNCTIONALITY .....................................................................................................27
3.7.1 SMPTE DESCRAMBLING AND WORD ALIGNMENT ..........................................................................................27
3.7.2 INTERNAL FLYWHEEL.........................................................................................................................................27
3.7.3 SWITCH LINE LOCK HANDLING ........................................................................................................................27
3.7.4 HVF TIMING SIGNAL GENERATION...................................................................................................................30
3.8 DVB-ASI FUNCTIONALITY....................................................................................................32
3.8.1 DVB-ASI 8B/10B DECODING AND WORD ALIGNMENT....................................................................................32
3.8.2 STATUS SIGNAL OUTPUTS ................................................................................................................................32
3.9 DATA THROUGH MODE......................................................................................................32
3.10 ADDITIONAL PROCESSING FUNCTIONS...............................................................................33
3.10.1 FIFO LOAD PULSE ............................................................................................................................................33
3.10.2 ANCILLARY DATA DETECTION AND INDICATION..........................................................................................34
3.10.3 SMPTE 352M PAYLOAD IDENTIFIER................................................................................................................36
3.10.4 AUTOMATIC VIDEO STANDARD AND DATA FORMAT DETECTION...............................................................36
3.10.5 ERROR DETECTION AND INDICATION............................................................................................................39
3.10.6 ERROR CORRECTION AND INSERTION ..........................................................................................................43
3.10.7 EDH FLAG DETECTION.....................................................................................................................................45
3.11 PARALLEL DATA OUTPUTS...............................................................................................46
3.11.1 PARALLEL DATA BUS BUFFERS ......................................................................................................................46
3.11.2 PARALLEL OUTPUT IN SMPTE MODE..............................................................................................................47
3.11.3 PARALLEL OUTPUT IN DVB-ASI MODE ...........................................................................................................47
3.11.4 PARALLEL OUTPUT IN DATA-THROUGH MODE.............................................................................................47
3.11.5 PARALLEL OUTPUT CLOCK (PCLK) ................................................................................................................47
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1561-CF 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
GS1561-CFT 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFTE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
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