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參數(shù)資料
| 型號： | GS1560ACFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進(jìn)程- R的第二雙率解串器 |
| 文件頁數(shù)： | 46/80頁 |
| 文件大?。?/td> | 842K |
| 代理商： | GS1560ACFE3 |
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GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
46 of 80
3.8.3 Status Signal Outputs
In DVB-ASI mode, the DOUT19 and DOUT18 pins will be configured as DVB-ASI
status signals SYNCOUT and WORDERR respectively.
SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output.
This output may be used to drive the write enable signal of an external FIFO, thus
providing a means of removing the K28.5 sync characters from the data stream.
Parallel DVB-ASI data may then be clocked out of the FIFO at some rate less than
27MHz. See
Figure 3-4
.
WORDERR will be high whenever the device has detected a running disparity error
or illegal code word.
Figure 3-4: DVB-ASI FIFO Implementation Using The GS1560A
3.9 Data Through Mode
The GS1560A/GS1561 may be configured by the application layer to operate as a
simple serial-to-parallel converter. In this mode, the device presents data to the
output data bus without performing any decoding, descrambling or
word-alignment.
Data through mode is enabled only when the MASTER/SLAVE, SMPTE_BYPASS,
and DVB_ASI input pins are set LOW. Under these conditions, the lock detection
algorithm enters PLL lock mode, (see
Lock Detect on page 35
), such that the
device may reclock data not conforming to SMPTE or DVB-ASI streams. The
LOCKED pin will indicated analog lock.
When operating in master mode, the GS1560A/GS1561 will set the
SMPTE_BYPASS and DVB_ASI signals to logic LOW if presented with a data
stream without SMPTE TRS ID words or DVB-ASI sync words. The LOCKED and
data bus outputs will be forced LOW and the serial digital loop-through output
(GS1560A only) will be a buffered version of the input.
3.10 Additional Processing Functions
The GS1560A/GS1561 contains an additional data processing block which is
available in SMPTE mode only, (see
SMPTE Functionality on page 38
).
8
8
AOUT ~ HOUT
WORDERR
PCLK = 27MHz
SYNCOUT
DDI
DDI
CLK_IN
CLK_OUT
FIFO
READ_CLK
<27MHz
FE
FF
TS
WE
WORDERR
GS1560A / GS1561
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1561-CF | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1561-CFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
| GS1561-CF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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