參數(shù)資料
型號: GS1535-CFU
廠商: Gennum Corporation
英文描述: GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker
中文描述: GS1535的HD - LINX進程二,商標(biāo)多速率SDI自動時鐘恢復(fù)器
文件頁數(shù): 14/22頁
文件大?。?/td> 238K
代理商: GS1535-CFU
GS1535 Data Sheet
18557 - 8
February 2005
14 of 22
3.2 VCO
The internal VCO of the GS1535 is a ring oscillator. It is trimmed at the time of
manufacture to capture all SD and HD data rates over temperature, and operation
voltage ranges.
Integrated into the VCO is a series of programmable dividers, to achieve all serial
data rates, as well as additional dividers for the frequency acquisition loop.
3.3 Charge Pump
A common charge pump is used for the GS1535’s PLL.
During frequency acquisition, the charge pump has two states, “pump-up” and
“pump-down” which is produced by a leading or lagging phase difference between
the input and the VCO frequency.
During phase acquisition, there are two levels of “pump-up” and two levels of
“pump down” produced for leading and lagging phase difference between the input
and VCO frequency. This is to allow for greater precision of VCO control.
The charge pump produces these signals by holding the integrated frequency
information on the external loop-filter capacitor, C
LF
.. The instantaneous
frequency information is the result of the current flowing through an internal resistor
connected to the loop-filter capacitor.
3.4 Frequency Acquisition Loop —The Phase-Frequency Detector
An external crystal of 14.140 MHz is used as a reference to keep the VCO centered
at the last known data rate. This allows the GS1535 to achieve a fast synchronous
lock, especially in cases where a known data rate is interrupted. The crystal
reference is also used to clock internal timers and counters. To keep the optimal
performance of the reclocker over all operating conditions, the crystal frequency
must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is
available from GENNUM.
The VCO is divided by a selected ratio which is dependant on the input data rate.
The resultant is then compared to the crystal frequency. If the divided VCO
frequency and the crystal frequency are within 1% of each other, the PLL is
considered to be locked to the input data rate.
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