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| 型號： | GPTRM |
| 英文描述： | General-Purpose Timer Reference Manual |
| 中文描述： | 通用定時器參考手冊 |
| 文件頁數(shù)： | 56/90頁 |
| 文件大?。?/td> | 647K |
| 代理商： | GPTRM |
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MOTOROLA
9-2
SPECIAL MODES
GPT
REFERENCE MANUAL
9.3 Freeze Mode
MCUs in Motorola's family of modular microcontrollers have an alternate operating
mode in addition to their normal mode. This mode is the background debug mode
(BDM). In BDM all normal processing is suspended and the user can view the contents
of registers and memory locations and can execute other operations. Refer to the ap-
propriate CPU manual to see what operations are available. BDM must be enabled at
reset before it can be entered.
Several sources within the MCU cause the CPU to go into background debug mode.
These sources can be an external breakpoint, the BGND instruction, or a double bus
fault. Refer to the appropriate CPU manual for details. When the CPU enters back-
ground debug mode, the FREEZE signal on the IMB and the FREEZE pin are assert-
ed. Assertion of FREEZE is the first indication that the CPU has entered BDM. While
in BDM, each module in the MCU can independently enter freeze mode.
While in freeze mode, a snapshot of most of the internal registers is available, and cer-
tain write operations not normally allowed can be executed. Freeze mode freezes the
current state of the timer. The prescaler and the pulse accumulator do not increment,
and changes to the pins while in freeze mode are ignored. (The input synchronizers
for the input pins are not clocked.) All other timer functions controlled by the CPU will
operate normally; for example, registers can be written to change pin directions, force
output compares, read or write I/O pins.
To enter freeze mode, the CPU must be in background debug mode, and the FRZ0 bit
in the GPT MCR must be set to a logic level one. The FRZ0 bit can be set prior to the
processor entering background debug mode. The FRZ1 bit can be read and written,
but has no function and is reserved for future use.
The prescaler and the pulse accumulator will remain stopped, and the input pins will
be ignored until the FREEZE signal is negated (the CPU is no longer in BDM), the
FRZ0 bit is negated or the MCU is reset. Activities begun prior to the entering of freeze
mode will be completed. For example, if an input edge on an input capture pin is de-
tected just as the FREEZE signal is asserted, the capture occurs, and the correspond-
ing interrupt flag is set. This occurs even if it takes a few clocks after the beginning of
freeze mode.
While the FREEZE signal is asserted, the CPU has write access to registers and bits
that are normally read-only, or write-once. The write-once bits can be written to as of-
ten as needed. It is not necessary for the FRZ0 bit to be set to allow write access to
these registers and bits.
9.4 Single Step Mode (STOPP and INCP)
Two bits in the module configuration register (MCR) allow debugging of the GPT with-
out the MCU entering BDM. As in freeze mode, the prescaler and the pulse accumu-
lator stop counting, and changes at input pins are ignored when the STOPP bit is
asserted. Reads of the GPT pins will return the state of the pin when the STOPP bit is
set. After the STOPP bit is set, the INCP bit can be used to increment the prescaler
and clock the input synchronizers once. The INCP bit is self-negating after the pres-
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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