參數(shù)資料
型號: GMS81524BK
廠商: Hynix Semiconductor Inc.
元件分類: 8位微控制器
英文描述: 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 8位單晶片微控制器
文件頁數(shù): 63/110頁
文件大?。?/td> 1980K
代理商: GMS81524BK
GMS81508B/16B/24B, GMS82512/16/24
60
MAY. 2001 Ver 2.0
16. INTERRUPTS
The GMS815xxB and GMS825xx interrupt circuits con-
sist of Interrupt enable register (IENH, IENL), Interrupt re-
quest flags of IRQH, IRQL, Priority circuit, and Master
enable flag (“I” flag of PSW). Thirteen interrupt(twelve
interrupt in case of GMS825xx) sources are provided. The
configuration of interrupt circuit is shown in Figure 16-2.
The External Interrupts INT0 ~ INT3 each can be transi-
tion-activated (1-to-0 or 0-to-1 transition) by selection
IEDS.
The flags that actually generate these interrupts are bit
INT0F, INT1F, INT2F and INT3F in register IRQH. When
an external interrupt is generated, the flag that generated it
is cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.
The Timer 0 ~ Timer 3 Interrupts are generated by TxIF
which is set by a match in their respective timer/counter
register. The Basic Interval Timer Interrupt is generated by
BITIF which is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADIF which is
set by finishing the analog to digital conversion.
The Watchdog timer Interrupt is generated by WDTIF
which set by a match in Watchdog timer register.
The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer counter register.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW on page 22), the interrupt enable
register (IENH, IENL), and the interrupt request flags (in
IRQH and IRQL) except Power-on reset and software
BRK interrupt. Below table shows the Interrupt priority.
*
This interrupt is NOT served on GMS825xx.
Vector addresses are shown in Figure 8-6 on page 24. In-
terrupt enable registers are shown in Figure 16-3. These
registers are composed of interrupt enable flags of each in-
terrupt source and these flags determines whether an inter-
rupt will be accepted or not. When enable flag is “0”, a
corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which dis-
ables all interrupts at once.
Figure 16-1 Interrupt Request Flag
Reset/Interrupt
Symbol
Priority
Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
ADC Interrupt
Basic Interval Timer
Watchdog Timer
*
Serial Communication
RESET
INT0
INT1
INT2
INT3
Timer 0
Timer 1
Timer 2
Timer 3
ADC
BIT
WDT
SCI
1
2
3
4
5
6
7
8
9
10
11
12
13
INT3IF
R/W
INT0IF
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
Timer/Counter 0 interrupt request flag
INITIAL VALUE: 0000 0000
B
ADDRESS: 0F7
H
IRQH
INT1IF
MSB
LSB
T2IF
T3IF
T0IF
T1IF
INT2IF
R/W
R/W
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
*
SIOIF
R/W
ADIF
Serial Communication interrupt request flag
INITIAL VALUE: 0000 ----
B
ADDRESS: 0F5
H
IRQL
WDTIF
MSB
LSB
-
-
-
BITIF
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
-
-
-
-
Basic Interval Timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
*
This is NOT served on GMS825xx.
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