
GL860A USB 2.0 UVC Camera Controller
2007 GenesysLogic, Inc. - All rights reserved.
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be cleared by SETUP transaction automatically.
Endpoint 0 transmitting stall.
Endpoint 0 will respond with a STALL to a valid IN transaction. This bit will be
cleared by SETUP transaction automatically.
2 EP0TXSTL
1 TX0OE
Ready to transmit control data.
0 TX0SEQ
Endpoint 0 transmission data toggle.
0 TX DATA0
1 TX DATA1
Offset 4Eh – RX0CNT ………………………………………………..………… Default value = 8’h00
CTLRD
RX0CNT6 RX0CNT5 RX0CNT4 RX0CNT3 RX0CNT2 RX0CNT1 RX0CNT0
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
7 CTLRD
Control pipe(Endpoint 0) control to prevent response of bulk packet.
0 Host send OUT packet right after SETUP package. (Has a IN packet status)
1 Host send IN packet right after SETUP package. (Has a OUT packet status)
6-0 RX0CNT[6:0]
The received DATA length of endpoint 0.
Offset 4Fh – FF0BUF ………………………………………………..………… Default value = 8’h00
FF0DAT7
FF0DAT6
FF0DAT5
FF0DAT4
FF0DAT3
FF0DAT2
FF0DAT1
FF0DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF0DAT[7:0]
Data entry for endpoint 0 FIFO.
Writing this register will push data into endpoint 0 TXFIFO, and reading will
pop data from endpoint 0 RXFIFO.
Offset 50h – FF1BUF ………………………………………………..………… Default value = 8’h00
FF1DAT7
FF1DAT6
FF1DAT5
FF1DAT4
FF1DAT3
FF1DAT2
FF1DAT1
FF1DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF1DAT[7:0]
Data entry for endpoint 1 FIFO.
Writing this register will push data into endpoint 1 TXFIFO, and reading will
pop data from endpoint 1 RXFIFO.
Offset 51h – FF2BUF ………………………………………………..………… Default value = 8’h00
FF2DAT7
FF2DAT6
FF2DAT5
FF2DAT4
FF2DAT3
FF2DAT2
FF2DAT1
FF2DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF2DAT[7:0]
Data entry for endpoint 2 FIFO.
Writing this register will push data into endpoint 2 TXFIFO, and reading will
pop data from endpoint 2 RXFIFO.