
GL860A USB 2.0 UVC Camera Controller
2007 GenesysLogic, Inc. - All rights reserved.
Page 21
7 SOF
SOF token packet received event
6 CHIRP_DET
Chirp sequence “K-J-K-J-K-J” detected.
5
SRST
USB Reset (SE0 for 3ms) is detected.
After receiving this event, uC should begin the HS detection handshake.
4 WAKEUP
Remote-wakeup event is detected during suspend state
3 RESUME
USB resume detected
2 SUSPD
USB suspend detected
1 EP0TX
Endpoint 0 transmits a data packet completely.
0 EP0RX
Endpoint 0 receives a data packet.
Offset 42h – UEVT2 ………………………………………………..…………… Default value = 8’h00
SETUP
TSTPKTX
EP2NAK
EP1NAK
EP0NAK
EP3TX
EP2RX
EP1TX
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
7 SETUP
Device received a setup packet.
6 TSTPKTX
Test Packet is sent complete.
5-3 EPnNAK
Endpoint receiving or transmitting NAK flag. (n=2~0)
2 EP3TX
Endpoint 3 transmission done event
1 EP2RX
Endpoint 2 receive done event.
0 EP1TX
Endpoint 1 transmission done event.
Offset 43h – UEVT1EN …………………………………………..…………… Default value = 8’h00
SOFEN
CHIRPDEN URSTEN
WKUPEN
RSMEN
SUSEN
EP0TXEN EP0RXEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0
These are the interrupt enable bits for USB event interrupt #1 to uC.
(Mask bits of USBEVT1)
Offset 44h – UEVT2EN …………………………………………..…………… Default value = 8’h00
SETUPEN
TSTPKTXEN
EP2NAKEN EP1NAKEN EP0NAKEN
EP3TXEN EP2RXEN EP1TXEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0
These are the interrupt enable bits for USB event interrupt #2 to uC.
(Mask bits of USBEVT1)
Offset 45h – UTMCTL …………………………………………..…………… Default value = 8’h0C
VMI
VPI
OPMOD1
OPMOD0
FSPEED
HSTERM
TXVLDH/
RXVLDH
R/W
TXVLD/
RXACTV
R/W
R/O
R/O
R/W
R/W
R/W
R/W
Write
To generate HS Chirp, set to 8’b0010_0111.
To generate FS Remote-Wake-Up, set to 8’b0010_1111.
Read
RXACTV/RXVLDH will reflect the real-time status of the UTM interface.