參數(shù)資料
型號(hào): GCIXP1250-200
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 36/148頁
文件大小: 1601K
代理商: GCIXP1250-200
Intel
IXP1250 Network Processor
36
Datasheet
EOP
AJ12
I1/TS
1
End of Packet Indication.
Receive End of Packet Input in 32-bit unidirectional IX
Bus mode.
Input/Output in 64-bit bidirectional IX Bus mode. EOP is
Transmit End of Packet output according to values
programmed in the TFIFO control field. Is Receive End
of Packet input during receive cycles.
In a shared IX Bus system, this pin will be tri-stated
when passing ownership of the IX Bus.
EOP32
AL7
O4
1
Transmit End Of Packet
32-bit unidirectional IX Bus modes EOP32 is Transmit End
of Packet output according to values programmed in the
TFIFO control field.
SOP32
AH8
O4
1
Transmit Start Of Packet Indication
Output in 32-bit unidirectional IX Bus modes. SOP32 is
Transmit Start of Packet output during transmit
according to values programmed in the TFIFO control
field.
TK_OUT
AA29
O1
1
Token Output.
Used to pass ownership of the IX Bus in a shared IX Bus
system in 64-bit bidirectional IX Bus mode.
In 32-bit unidirectional mode this bit is unused and should be
left unconnected.
TK_IN
AA28
I1
1
Token Input.
64-bit bidirectional IX Bus Mode: A high-to-low transition
indicates that this device has been given ownership of the IX
Bus in a shared IX Bus system.
In 32-bit unidirectional mode, this input is not used and
should be pulled high.
During Reset, used to configure the device as initial IX Bus
owner. 1= device is initial owner, 0= device does not own the
IX Bus. TK_IN is sampled from the rising edge of
RESET_IN_L.
Totals:
103
Table 15. IX Bus Interface Pins (Continued)
IX Bus Signal
Names
Pin
Number
Type
Total
Pin Descriptions
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