High Performance E2CMOS PLD Generic Array Logic 1 2 20 I/CLK I Vcc " />
參數(shù)資料
型號(hào)： GAL18V10B-10LP
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 8/15頁(yè)
文件大小： 0K
描述： IC PLD 10MACRO 5.0V 10NS 20PDIP
標(biāo)準(zhǔn)包裝： 18
系列： GAL®18V10
可編程類型： EE PLD
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 4.75 V ~ 5.25 V
宏單元數(shù)： 10
工作溫度： 0°C ~ 75°C
安裝類型： 通孔
封裝/外殼： 20-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 20-PDIP
包裝： 管件
GAL18V10
High Performance E2CMOS PLD
Generic Array Logic
1
2
20
I/CLK
I
Vcc
I/O/Q
I
GND
I/O/Q I/O/Q
I/O/Q
4
6
8
9
11
13
14
16
18
1
10
11
20
I/CLK
I
I/O/Q
GND
Vcc
I/O/Q
5
15
GAL18V10
Top View
GAL
18V10
DIP
PLCC
I/O/Q
I/CLK
RESET
PRESET
8
10
8
OLMC
I
PROGRAMMABLE
AND-ARRAY
(96X36)
Copyright 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
November 2003
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
18v10_04
Features
HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS Advanced CMOS Technology
LOW POWER CMOS
— 75 mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs
PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E2 technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
ALL
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GAL18V10B15LJ 制造商:LATTICE 功能描述:*
GAL18V10B-15LJ 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 18 INPUT 10 OUTPUT 5 V LOW POWER 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
GAL18V10B-15LJN 制造商:Lattice Semiconductor Corporation 功能描述:SPLD GAL Family 10 Macro Cells 66.7MHz 5V 20-Pin PLCC
GAL18V10B15LP 制造商:Lattice Semiconductor Corporation 功能描述:
GAL18V10B-15LP 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 18 Input 10 Output 5V Low Power 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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