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參數(shù)資料
| 型號： | GAL18V10B-10LP |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD 10MACRO 5.0V 10NS 20PDIP |
| 標準包裝： | 18 |
| 系列： | GAL®18V10 |
| 可編程類型： | EE PLD |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 10 |
| 工作溫度： | 0°C ~ 75°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
Specifications GAL18V10
11
Typical Input
Typical Output
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
(Vref Typical = 3.2V)
Circuitry within the GAL18V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1μs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
Device Pin
Reset to Logic "0"
Vc c
CL K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Power-Up Reset
Input/Output Equivalent Schematics
ALL
DEVICES
DISCONTINUED
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GAL18V10B15LJ | 制造商:LATTICE 功能描述:* |
| GAL18V10B-15LJ | 功能描述:SPLD - 簡單可編程邏輯器件 18 INPUT 10 OUTPUT 5 V LOW POWER 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL18V10B-15LJN | 制造商:Lattice Semiconductor Corporation 功能描述:SPLD GAL Family 10 Macro Cells 66.7MHz 5V 20-Pin PLCC |
| GAL18V10B15LP | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL18V10B-15LP | 功能描述:SPLD - 簡單可編程邏輯器件 18 Input 10 Output 5V Low Power 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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