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參數(shù)資料
| 型號： | G768D |
| 英文描述： | ± 3oC remote thermal sensor with one fan control and SMBus interface.|Thermal Sensor / Detector Series |
| 中文描述： | ± 3oC遠程溫度傳感器一個風扇控制和SMBus接口。|熱傳感器/探測器系列 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 323K |
| 代理商： | G768D |
Ver: 1.4
May 23, 2003
TEL: 886-3-5788833
http://www.gmt.com.tw
14
G768D
Global Mixed-mode Technology Inc.
To check for internal bus collisions, read the status
byte. If the least significant seven bits are ones, dis-
card the data and read the status byte again. The
status bits LHIGH, LLOW, RHIGH, and RLOW are
refreshed on the SMBus clock edge immediately fol-
lowing the stop condition, so there is no danger of
losing temperature-related status data as a result of
an internal bus collision. The OPEN status bit (diode
continuity fault) is only refreshed at the beginning of a
conversion, so OPEN data is lost. The ALERT inter-
rupt latch is independent of the status byte register, so
no false alerts are generated by an internal bus colli-
sion.
When auto-converting, if the THIGH and TLOW limits
are close together, it's possible for both high-temp and
low-temp status bits to be set, depending on the
amount of time between status read operations (espe-
cially when converting at the fastest rate). In these
circumstances, it's best not to rely on the status bits to
indicate reversals in long-term temperature changes
and instead use a current temperature reading to es-
tablish the trend direction.
Temperature Conversion Rate Byte
The conversion rate register (Table 7) programs the
time interval between conversions in free running
auto-convert mode. This variable rate control reduces
the supply current in portable-equipment applications.
The conversion rate byte's POR state is 02h (0.25Hz).
The G768D looks only at the 3 LSB bits of this register,
so the upper 5 bits are "don't care" bits, which should
be set to zero. The conversion rate tolerance is ±25%
at any rate setting.
Valid A/D conversion results for all channels are avail-
able one total conversion time (125ms nominal, 156ms
maximum) after initiating a conversion, whether con-
version is initiated via the RUN/STOP bit, one-shot
command, or initial power-up. Changing the conver-
sion rate can also affect the delay until new results are
available. See Table 8.
Programmed fan speed register
The programmed fan speed register 10h is read / write
register. They contain the count number of the desired
fan speed. Power up default is FFh.
Actual fan speed register
The actual fan speed register 11h is read only. They
contain the count number of the actual fan speed.
Power up default is FFh.
Fan status register
The fan status registers 12h is read only. Its bit 0 is set
to 1 when the actual fan speed is ±20% outside the
desired speed. Its bit 1 is set to 1 when fan speed is
below 1920 rpm. Power up default is 0000_0010b.
Watchdog for fan control
Four temperature threshold registers intervene the
control of fan. Pin FANVCC go high when one of the
remote temperature, DX1 and DX2, rises above the
respective TMAX. The control is not released until
both temperature values drop below their THYST Be-
sides, the fan controller also fully turns on the fan
when either of the two remote diodes is open or both
are short.
The power-up default values for TMAX and THYST
are +70°C and +60°C, respectively. This allows the
G768D to be used in the occasion when system fails
and loses the fan control of G768D.
Slave Addresses
The G768D appears to the SMBus as one device hav-
ing a common address for all the ADC and fan control
channels. The device address is fixed to be 7Ah for
write and 7Bh for read.
The G768D also responds to the SMBus Alert Re-
sponse slave address (see the Alert Response Ad-
dress section).
POR and UVLO
The G768D has a volatile memory. To prevent am-
biguous power-supply conditions from corrupting the
data in memory and causing erratic behavior, a POR
voltage detector monitors V
CC
and clears the memory
if V
CC
falls below 1.7V (typical, see Electrical Charac-
teristics table). When power is first applied and V
CC
rises above 1.75V (typical), the logic blocks begin op-
erating, although reads and writes at V
CC
levels below
3V are not recommended. A second V
CC
comparator,
the ADC UVLO comparator, prevents the ADC from
converting until there is sufficient headroom (V
CC
=
2.8V typical).
Power-Up Defaults:
Interrupt latch is cleared.
ADC begins auto /converting at a 0.25Hz rate.
Command byte is set to 00h to facilitate quick re-
mote Receive Byte queries.
THIGH and TLOW registers are set to max and
min limits, respectively
Detection On fan Failure
Setting bit 5 (DET_FAN) of CONFIGURATION-BYTE
register with logic 1 activates the detection of fan fail-
ure. G768D detects fan failure via FG pin. G768D de-
fines fan failure as no transition on FG pin for about
0.5sec or the fan measurement result is 255 counts for
consecutive 8 times, it takes about 0.25sec. Once fan
failure is detected the ALERT# will be set to logic low
and the bit 0 (FAN_FAIL) of STATUS-BYTE will be set
to logic high.
To clear the ALERT# signal caused by fan failure, the
DET_FAN bit should be set to 0 then issue an ARA
command on serial bus.
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