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| 型號： | G4WP |
| 英文描述： | G4 Architecture White Paper |
| 中文描述： | 四國集團架構(gòu)白皮書 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 100K |
| 代理商： | G4WP |
4
Benefit 7. Dual-Ported L1 Data Cache
Tags
In a dual-PowerPC architecture or a system with
one PowerPC processor and an additional system
bus master, bus snooping is required to maintain
coherency of data throughout the system. In the
MPC750, if a snoop is blocked because the data tag
is being accessed, the MPC750 must assert ARTRY,
notifying the current bus master to abort the
transaction and retry it later. The G4 architecture
eliminates this inef
fi
ciency by implementing
dual-ported L1 data tags. In the MPC74xx devices,
the bus snoop can proceed without being blocked
by a simultaneous access to the tags.
Benefit 8. Shared Cache State for Data
The MPC750 has an MEI cache coherency
mechanism, including Modi
fi
ed (M), Exclusive (E),
and Invalid (I) states for entries in the data cache.
Consider a dual-processor design using G3 devices
which we’ll identify as A and B. When A’s read
transaction generates a cache line
fi
ll, the incoming
block is allocated as Exclusive in A’s cache. If B
snooped A’s read transaction and detected a
Modi
fi
ed copy of the same block in cache, B would
have responded by pushing the cache block to
memory (and marking the line Invalid) so that A
would access the latest data during its cache line
fi
ll.
The next time B needs that data, however, B has to
read the line from memory. Even worse, if A has
modi
fi
ed the data in its cache by the time B is ready
to read it, the very same snoop sequence would be
repeated in reverse. That is, B would have to wait
for A to push the data to memory before retrieving
it. Each of these cache block pushes consumes
much-needed data bus bandwidth.
The MPC7400/7410 and MPC7440/MPC7450
have a 4-state cache coherency mechanism known
as MESI. The additional cache state is Shared (S),
and it is associated with a new 60x bus signal called
SHD. The new Shared state gives both processors in
a dual-processor system the capability to maintain a
valid copy of the same cache line simultaneously. In
the case of a read transaction by A and a snoop by
B, processor B would respond with an assertion of
SHD to notify A that this block has already been
cached elsewhere in the system. Processor A would
then load the incoming block into its own cache as
Shared, and B would change its cache block’s state
from Exclusive to Shared. Now both processors can
access the shared data without the need for a retry
transaction or snoop push. By limiting bus accesses,
the Shared capability signi
fi
cantly improves
performance in a symmetric multi-processing
system.
Benefit 9. Easy Upgrade from MPC750
The MPC7410 (Rev 1.4) has the same 3.3V I/O
supply voltage as the MPC750 on the system bus.
This consistency enables the MPC7410 to replace
the
MPC750
while
compatibility with existing logic on the PowerPC
system bus. Burst SRAMs are readily available at
the lower I/O voltage of the MPC7410’s L2 bus.
providing
electrical
The MPC7400/MPC7410 also has the same
footprint as the MPC750. One new signal, L2VSEL
(previously a No-Connect on the MPC750), is used
in a MPC7410-based system to select the desired
L2 bus voltage of 2.5V or 1.8V. Another
No-Connect signal on the MPC750 is used as
BVSEL to select the desired system bus voltage
(3.3V, 2.5V, or 1.8V) for the MPC7410. The
MPC7400/MPC7410’s SHD pin (described in
Bene
fi
t 8) is also implemented on one of the
MPC750’s No-Connect pins. With just a few
hardware modi
fi
cations, the MPC7400/MPC7410
is an easy drop-in replacement for the MPC750.
[For details on the signal differences between the
MPC750, MPC7400/7410, and MPC7440/7450
implementations, please refer to the “PowerPC 60x
Bus Implementation Differences Application
Note.” See “References” below.]
The core voltage is lower in the MPC74xx devices
than in the MPC750; however, this reduction,
combined with the smaller submicron geometry,
enables G4 devices to achieve higher operating
frequencies and improved I/O performance, while
minimizing the increase in power consumption.
For a uni-processor architecture, there is no need to
implement G4’s optional bus signals, which could
be used in MPX bus mode to support SMP (for
features such as intervention and snar
fi
ng).
And
fi
nally, G3 and G4 devices share a common
debug architecture, so the same extensive tools
support is available for MPC750 and MPC74xx
processors.
Benefit 10. G4 is from Motorola
Motorola’s commitment to the scaleability of the
PowerPC architecture is reinforced with each
high-performance product we add to the family.
The MPC74xx devices are no exceptions. G4
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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