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參數(shù)資料
| 型號： | FXLH1T45L6X |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRANSLATOR 1BIT BIDIR 6MICROPAK |
| 產(chǎn)品培訓(xùn)模塊： | Logic Translator Solutions |
| 產(chǎn)品變化通告： | Die Material, Mold Compound Change 03/Oct/2008 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 邏輯功能： | 變換器，雙向，3 態(tài) |
| 位數(shù)： | 1 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 3.5ns |
| 電源電壓： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 6-UFDFN |
| 供應(yīng)商設(shè)備封裝： | Micro6?（TSOP-6） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1220 (CN2011-ZH PDF) |
| 其它名稱： | FXLH1T45L6XDKR FXLH1T45L6XDKR-ND FXLH1T45L6XFSDKR |
FXLH1T45
Lo
w
V
olta
g
e
1-Bit
Bi-directional
Level
T
ranslator
with
Con
gurab
le
V
olta
g
e
Supplies
and
Bushold
Data
Inputs
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLH1T45 Rev. 1.0.4
7
AC Electrical Characteristics (Continued)
VCCA = 1.4V to 1.6V
VCCA = 1.1V to 1.3V
Note:
8. The enable time, tPZH or tPZL, is the time for the FXLH1T45 to return to active operation after a direction change. The enable time
species the worst-case delay from the time the T/R pin is switched until a valid output signal is expected. For example, to change
direction to B-to-A operation, the T/R pin is switched from HIGH-to-LOW. The enable time for this case is found by adding the
disable time for T/R to B to the propagation delay for B to A. The formulas for calculating enable times are the following:
tPZH (T/R to A) = tPLZ (T/R to B) + tPLH (B to A)
tPZL (T/R to A) = tPHZ (T/R to B) + tPHL (B to A)
tPZH (T/R to B) = tPLZ (T/R to A) + tPLH (A to B)
tPZL (T/R to B) = tPHZ (T/R to A) + tPHL (A to B)
Capacitance
Symbol
Parameter
TA = 40°C to +85°C
Units
VCCB =
3.0V to 3.6V
VCCB =
2.3V to 2.7V
VCCB =
1.65V to
1.95V
VCCB =
1.4V to 1.6V
VCCB =
1.1V to 1.3V
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay A to B
0.5
4.3
0.5
4.8
1.0
6.0
1.0
7.3
1.5
22.0
ns
Propagation Delay B to A
0.6
6.8
0.8
6.9
0.9
7.1
1.0
7.3
1.3
9.5
tPZH, tPZL
(8)
Output Enable
T/R to B
1.5
10.3
1.5
10.8
2.0
12.0
2.0
13.3
2.5
28.0
ns
Output Enable
T/R to A
1.0
12.9
1.2
13.1
1.8
13.3
2.5
14.8
3.3
27.5
tPHZ, tPLZ
Output Disable
T/R to B
0.4
6.1
0.4
6.2
0.9
6.2
1.5
7.5
2.0
18.0
ns
Output Disable
T/R to A
1.0
6.0
1.0
6.0
1.0
6.0
1.0
6.0
1.0
6.0
Symbol
Parameter
TA = 40°C to +85°C
Units
VCCB =
3.0V to 3.6V
VCCB =
2.3V to 2.7V
VCCB =
1.65V to
1.95V
VCCB =
1.4V to 1.6V
VCCB =
1.1V to 1.3V
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay A to B
0.8
13.0
1.0
7.0
1.2
8.0
1.3
9.5
2.0
24.0
ns
Propagation Delay B to A
1.4
22.0
1.4
22.0
1.5
22.0
1.5
22.0
2.0
24.0
tPZH, tPZL
(8)
Output Enable
T/R to B
2.8
28.0
3.0
19.0
3.2
20.0
3.3
21.5
4.0
36.0
ns
Output Enable
T/R to A
2.4
37.0
2.1
29.0
2.5
30.0
3.5
32.0
4.0
44.0
tPHZ, tPLZ
Output Disable
T/R to B
1.0
15.0
0.7
7.0
1.0
8.0
2.0
10.0
2.0
20.0
ns
Output Disable
T/R to A
2.0
15.0
2.0
12.0
2.0
12.0
2.0
12.0
2.0
12.0
Symbol
Parameter
Conditions
TA = +25°C
Units
Typical
CIN
Input Capacitance Control Pin (T/R)VCCA = VCCB = 3.3V, VI = 0V or VCCA/B
4.0
pF
CI/O
Input/Output Capacitance An, Bn Ports VCCA = VCCB = 3.3V, VI = 0V or VCCA/B
5.0
pF
CPD
Power Dissipation Capacitance
VCCA = VCCB = 3.3V, VI = 0V or VCC,
F
= 10MHz
20.0
pF
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