參數(shù)資料
型號： FXLH1T45L6X
廠商： Fairchild Semiconductor
文件頁數(shù)： 4/11頁
文件大?。?/td> 0K
描述： TRANSLATOR 1BIT BIDIR 6MICROPAK
產(chǎn)品培訓(xùn)模塊： Logic Translator Solutions
產(chǎn)品變化通告： Die Material, Mold Compound Change 03/Oct/2008
標(biāo)準(zhǔn)包裝： 1
邏輯功能： 變換器，雙向，3 態(tài)
位數(shù)： 1
輸入類型： 電壓
輸出類型： 電壓
通道數(shù)： 1
輸出/通道數(shù)目： 1
差分 - 輸入:輸出： 無/無
傳輸延遲（最大）： 3.5ns
電源電壓： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 6-UFDFN
供應(yīng)商設(shè)備封裝： Micro6?（TSOP-6）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1220 (CN2011-ZH PDF)
其它名稱： FXLH1T45L6XDKR
FXLH1T45L6XDKR-ND
FXLH1T45L6XFSDKR
FXLH1T45
Lo
w
V
olta
g
e
1-Bit
Bi-directional
Level
T
ranslator
with
Con
gurab
le
V
olta
g
e
Supplies
and
Bushold
Data
Inputs
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLH1T45 Rev. 1.0.4
2
Functional Diagram
Connection Diagram
(Top Through View)
Pin Assignment
Pin Descriptions
Function Table
H
= HIGH Logic Level
L
= LOW Logic Level
Power-Up/Power-Down Sequencing
FXL translators offer an advantage in that either VCC
may be powered up rst. This benet derives from the
chip design. When either VCC is at 0V, outputs are in a
HIGH-Impedance state. To ensure that bus contention,
excessive currents, or oscillations do not occur, a proper
power-up sequence is recommended.
The recommended power-up sequence is the following:
1. Apply power to either VCC.
2. Apply power to the T/R input (Logic HIGH for A-to-B
operation; Logic LOW for B-to-A operation) and to the
respective data inputs (A Port or B Port). This may
occur at the same time as Step 1.
3. Apply power to other VCC.
The recommended power-down sequence is the follow-
ing:
1. Remove power from either VCC.
2. Remove power from other VCC.
Pin Number
Terminal Name
1VCCA
2
GND
3A
4B
5
T/R
6VCCB
Pin Names
Description
T/R
Transmit/Receive Input
A
Side A Input or Output
B
Side B Input or Output
VCCA
Side A Power Supply
VCCB
Side B Power Supply
VCCA
A
T/R
VCCB
B
1
2
34
6
5
VCCB
T/R
B
VCCA
GND
A
Inputs (T/R)
Outputs
L
Bus B Data to Bus A
H
Bus A Data to Bus B
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