參數(shù)資料
型號: FXLA104UMX
廠商: Fairchild Semiconductor
文件頁數(shù): 9/18頁
文件大?。?/td> 0K
描述: TRANSLATOR 4BIT DUAL LV 16UMLP
標(biāo)準(zhǔn)包裝: 1
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 4
輸入類型: 電壓
輸出類型: 電壓
數(shù)據(jù)速率: 140Mbps
通道數(shù): 1
輸出/通道數(shù)目: 4
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 4ns
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-UMLP
供應(yīng)商設(shè)備封裝: 16-UMLP(1.8x2.6)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: FXLA104UMXDKR
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLA104 Rev. 1.0.9
17
FXLA104
Low-Voltage
Dual-Suppl
y
4-Bit
Voltage
Translator
Physical Dimensions
Figure 13.12-Lead, UMLP, QUAD, JEDEC MO-252 1.8 x 1.8mm Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
A
B
C
SEATING
PLANE
RECOMMENDED
LAND PATTERN
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP12Arev4.
SCALE : 2X
LEAD
OPTION 1
SCALE : 2X
LEAD
OPTION 2
DETAIL A
SCALE : 2X
PIN#1 IDENT
TOP VIEW
BOTTOM VIEW
0.10 C
0.08 C
0.10 C
2X
SIDE VIEW
0.10 C
0.05
0.00
3
6
1
0.10 CA B
0.05 C
0.55 MAX.
12
1.80
0.40
0.25
0.15(12X)
0.35
0.45
2.10
0.40
0.563
(11X)
0.20
(12X)
1
0.152
9
0.588
DETAIL A
PIN#1 IDENT
(11X)
PACKAGE
EDGE
0.10
0.45
0.35
0.10
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