參數(shù)資料
型號: FXLA104UMX
廠商: Fairchild Semiconductor
文件頁數(shù): 14/18頁
文件大?。?/td> 0K
描述: TRANSLATOR 4BIT DUAL LV 16UMLP
標準包裝: 1
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 4
輸入類型: 電壓
輸出類型: 電壓
數(shù)據(jù)速率: 140Mbps
通道數(shù): 1
輸出/通道數(shù)目: 4
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 4ns
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-UMLP
供應商設備封裝: 16-UMLP(1.8x2.6)
包裝: 標準包裝
其它名稱: FXLA104UMXDKR
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLA104 Rev. 1.0.9
5
FXLA104
Low-Voltage
Dual-Suppl
y
4-Bit
Voltage
Translator
Power-Up/Power-Down Sequence
FXL translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0V, outputs are in a
high-impedance state. The control input (/OE) is
designed to track the VCCA supply. A pull-up resistor
tying /OE to VCCA should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up or power-down. The size of the
pull-up resistor is based upon the current-sinking
capability of the device driving the /OE pin.
The recommended power-up sequence is:
1.
Apply power to the first VCC.
2.
Apply power to the second VCC.
3.
Drive the /OE input LOW to enable the device.
The recommended power-down sequence is:
1.
Drive /OE input HIGH to disable the device.
2.
Remove power from either VCC.
3.
Remove power from other VCC.
Pull-Up/Pull-Down Resistors
Do not use pull-up or pull-down resistors. This device
has bus-hold circuits: pull-up or pull-down resistors are
not recommended because they interfere with the
output state. The current through these resistors may
exceed the hold drive, II(HOLD) and/or II(OD) bus-hold
currents, resulting in data transition and/or auto-
direction
sensing
failures.
The
bus-hold
feature
eliminates the need for extra resistors.
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