參數(shù)資料
型號: FW82801E
廠商: Intel Corp.
英文描述: Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述: 英特爾82801E通訊I / O控制器集線器(丙,出血)
文件頁數(shù): 42/84頁
文件大?。?/td> 1196K
代理商: FW82801E
Intel
82801E C-ICH
42
Advance Information Datasheet
3.2.9
USB Interface
3.2.10
Power Signals
Table 15. USB Interface Signals
Name
Type
Description
USBP0P
USBP0N
USBP1P
USBP1N
I/O
Universal Serial Bus Port 1:0 Differential:
These differential pairs are used to
transmit Data/Address/Command signals for ports 0 and 1.
OC[1:0]#
I
Overcurrent Indicators:
These signals set corresponding bits in the USB
controllers to indicate that an overcurrent condition has occurred.
Table 16. Power Signals
Name
Type
Description
PWROK
I
Power OK:
When asserted, PWROK is an indication to the 82801E C-ICH that
core power and PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, the 82801E C-ICH asserts PCIRST#.
RSM_PWROK
I
Resume Well Power OK:
When asserted, this signal is an indication to the
82801E C-ICH that the resume well power has been stable for at least 10 ms.
NOTE:
The 82801E C-ICH does not use the resume well power OK signal.
RSMRST#
I
Resume Well Reset:
RSMRST# is used for resetting the resume power plane
logic.
NOTE:
The 82801E C-ICH does not use the resume well reset signal.
VRMPWRGD
I
VRM Power Good:
VRMPWRGD should be connected to be the processor’s VRM
Power Good.
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