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參數(shù)資料
| 型號： | FT4232HQ-TRAY |
| 廠商： | FTDI, Future Technology Devices International Ltd |
| 文件頁數(shù)： | 6/45頁 |
| 文件大小： | 0K |
| 描述： | IC USB HS QUAD UART/SYNC 64-QFN |
| 標準包裝： | 260 |
| 系列： | USBmadeEZ-FIFO |
| 特點： | USB 至 UART 和（或）SPI、I2C、JTAG |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 2048 字節(jié) |
| 規(guī)程： | RS232，RS422，RS485 |
| 電源電壓： | 3 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN 裸露焊盤（9x9） |
| 包裝： | 托盤 |
| 配用： | 768-1031-ND - MOD USB HS FT4232H EVAL |
| 其它名稱： | FT4232HQ - TRAY |
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Copyright 2010 Future Technology Devices International Limited
14
Document No.: FT_000060
FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC
Datasheet Version 2.2
Clearance No.: FTDI#78
3.4.3 FT4232H pins used in an MPSSE
The FT4232H channel A and channel B each have a Multi-Protocol Synchronous Serial Engine (MPSSE).
Each MPSSE can be independently configured to a number of industry standard serial interface protocols
such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is
possible to use one of the FT4232H’s channels (e.g. channel A) to connect to an SRAM configurable FPGA
such as supplied by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no
defined function) at power-up. Application software on the PC could use the MPSSE to download
configuration data to the FPGA over USB. This data would define the hardware function on power up. The
other MPSSE channel (e.g. channel B) would be available for another serial interface function while
channel C and channel D can be configured as UART or bit-bang mode. Alternatively each MPSSE can be
used to control a number of GPIO pins. When configured in this mode, the pins used and the descriptions
of the signals are shown in Table 3.7
Channel A
Pin No.
Channel B
Pin No.
Name
Type
MPSSE Configuration Description
16
26
TCK/SK
OUTPUT
Clock Signal Output. For example:
JTAG – TCK, Test interface clock
SPI – SK, Serial Clock
17
27
TDI/DO
OUTPUT
Serial Data Output. For example:
JTAG – TDI, Test Data Input
SPI – DO, serial data output
18
28
TDO/DI
INPUT
Serial Data Input. For example:
JTAG – TDO, Test Data output
SPI – DI, Serial Data Input
19
29
TMS/CS
OUTPUT
Output Signal Select. For example:
JTAG – TMS, Test Mode Select
SPI – CS, Serial Chip Select
21
30
GPIOL0
I/O
General Purpose input/output
22
32
GPIOL1
I/O
General Purpose input/output
23
33
GPIOL2
I/O
General Purpose input/output
24
34
GPIOL3
I/O
General Purpose input/output
Table 3.7 Channel A and Channel B MPSSE Configured Pin Descriptions
For a functional description of this mode, please refer to section 4.4.
When either Channel A or Channel B or both channels are used in MPSSE mode, Channel C and Channel
D can be configured as asynchronous serial interface (RS232/422/485) or Bit-Bang mode or a
combination of both.
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