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參數(shù)資料
| 型號： | FT4232HQ-TRAY |
| 廠商： | FTDI, Future Technology Devices International Ltd |
| 文件頁數(shù)： | 13/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC USB HS QUAD UART/SYNC 64-QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | USBmadeEZ-FIFO |
| 特點： | USB 至 UART 和（或）SPI、I2C、JTAG |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 2048 字節(jié) |
| 規(guī)程： | RS232，RS422，RS485 |
| 電源電壓： | 3 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN 裸露焊盤（9x9） |
| 包裝： | 托盤 |
| 配用： | 768-1031-ND - MOD USB HS FT4232H EVAL |
| 其它名稱： | FT4232HQ - TRAY |
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Copyright 2010 Future Technology Devices International Limited
20
Document No.: FT_000060
FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC
Datasheet Version 2.2
Clearance No.: FTDI#78
4.4 MPSSE Interface Mode Description.
MPSSE Mode is designed to allow the FT4232H to interface efficiently with synchronous serial protocols
such as JTAG, I2C and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The
MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous serial
protocol (industry standard or proprietary) to be implemented using the FT4232H. MPSSE is only
available on channel A and channel B.
MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can
be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of
30 Mbits/s.
When a channel is configured in MPSSE mode, the IO timing and signals used are shown in Figure 4.4
and Table 4.1. These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to be provide a
slower clock.
Figure 4.4 MPSSE Signal Waveforms
NAME
MIN
NOM
MAX
Units
COMMENT
t1
33.33
ns
CLKOUT period
t2
15
16.67
ns
CLKOUT high period
t3
15
16.67
ns
CLKOUT low period
t4
1
7.15
ns
CLKOUT to TDI/DO delay
t5
0
ns
TDO/DI hold time
t6
11
TDO/DI setup time
Table 4.1 MPSSE Signal Timings
MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and a
hex value of 0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the
FT2232D” for more details and examples.
The MPSSE command set is fully described in application note AN_108 – “Command Processor For
MPSSE and MCU Host Bus Emulation Modes”.
The following additional application notes are available for configuring the MPSSE :
AN_109 – “Programming Guide for High Speed FTCI2C DLL”
AN_110 – “Programming Guide for High Speed FTCJTAG DLL”
AN_111 – “Programming Guide for High Speed FTCSPI DLL”
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