參數(shù)資料
型號: FT245BQ
廠商: Electronic Theatre Controls, Inc.
英文描述: FT245BQ USB FIFO ( USB - Parallel ) I.C.
中文描述: FT245BQ USB先進(jìn)先出(USB端口-并行)集成電路
文件頁數(shù): 10/24頁
文件大?。?/td> 505K
代理商: FT245BQ
DS245BL Version 1.6 Future Technology Devices Intl. Ltd. 2005
Page 10 of 24
FT245BL USB FIFO ( USB - Parallel ) I.C.
POWER AND GND GROUP
Pin#
Signal
6
3V3OUT
Type
OUT
Description
3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled
to GND using a 33nF ceramic capacitor in close proximity to the device pin. Its
prime purpose is to provide the internal 3.3V supply to the USB transceiver cell
and the RSTOUT# pin. A small amount of current (<= 5mA) can be drawn from
this pin to power external 3.3V logic if required.
+4.35 volt to +5.25 volt VCC to the device core, LDO and none-FIFO interface
pins.
+3.0 volt to +5.25 volt VCC to the FIFO interface pins 10..12, 14..16 and 18..25.
When interfacing with 3.3V external logic in a bus powered design connect
VCCIO to a 3.3V supply generated from the USB bus. When interfacing with
3.3V external logic in a self powered design connect VCCIO to the 3.3V supply
of the external logic. Otherwise connect to VCC to drive out at 5V CMOS level.
Device - Ground Supply Pins
Device - Analog Power Supply for the internal x8 clock multiplier
Device - Analog Ground Supply for the internal x8 clock multiplier
3,26
VCC
PWR
13
VCCIO
PWR
9,17
30
29
GND
AVCC
AGND
PWR
PWR
PWR
Note 1 :
In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
Note 2:
During device reset, these pins are tri-state but pulled up to VCCIO via internal 200K resistors.
Note 3:
During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.
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