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參數(shù)資料
| 型號： | FSSD07UMX_F113 |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX SD/SDIO MMC 75MHZ 24-MLP |
| 標準包裝： | 5,000 |
| 類型： | 多路復用器 |
| 應用： | 手機，數(shù)碼相機，媒體播放器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-UFQFN |
| 供應商設備封裝： | 24-UMLP |
| 包裝： | 帶卷 (TR) |
2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSSD07 Rev. 1.0.2
8
FSSD07
—
1-Bit
/
4-Bit
SD/SDIO
and
MMC
Dual-Host
Multiplexer
AC Electrical Characteristics at 1.8V VDDC
All typical values are for VDDC=1.8V at 25°C unless otherwise specified.
Symbol
Parameter
VDDC (V)
VDDH1 /
VDDH2 (V)
Conditions
TA=-40 to +85°C
Unit
Min. Typ. Max.
tON
Turn-On Time,
S, OE to CMD, DAT[3:0]
1.65 to 1.95 1.65 to 3.6
VSW=0V, RL=1k,
CL=20pF
Figure 7, Figure 8
8
18
ns
tOFF
Turn-Off Time,
S, OE to CMD, DAT[3:0]
1.65 to 1.95 1.65 to 3.6
VSW=0V, RL=1k,
CL=20pF
Figure 7, Figure 8
6
13
ns
tRISE1/
FALL1
CMD/DAT Output Edge Rates
(9)
1.65 to 1.95 1.65 to 3.6
RL=1k, CL=20pF
(10-90%)
Figure 7, Figure 8
3
ns
tPD
Switch Propagation Delay
(9)
1.65 to 1.95 1.65 to 3.6
RL=1k, CL=20pF
Figure 7, Figure 89
4.5
9
ns
tpLH
LH Propagation Delay 1CLK, 2CLK
to CLK
1.65 to 1.95 1.65 to 3.6
CL=20pF
Figure 10, Figure
11
4
6
ns
tpHL
HL Propagation Delay 1CLK, 2CLK
to CLK
1.65 to 1.95 1.65 to 3.6
CL=20pF
Figure 10, Figure
11
4
6
ns
tRISE2/
FALL2
CLK Output Edge Rates
(9)
1.65 to 1.95 1.65 to 3.6
CL=20pF (10-90%)
Figure 7, Figure 8
3
ns
OIRR
Off Isolation
(9)
1.8
1.65 to 3.6
f=10MHz, RT=50,
CL=20pF,
Figure 12
-60
dB
Xtalk
Non-Adjacent Channel Crosstalk
(9)
1.8
1.65 to 3.6
f=10MHz, RT=50,
CL=20pF,
Figure 13
-60
dB
ftoggle
Clock Frequency
(9)
1.8
1.65 to 3.6 CL=20pF
75
MHz
Note:
9.
Guaranteed by characterization, not production tested.
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