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參數(shù)資料
| 型號： | FS6128-07-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN W/VXCO 8-SOIC |
| 標準包裝： | 3,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 27MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
FS6128-07
VCXO
FS6128-07
PLL
XOUT
XIN
CLK
XTUNE
DIVIDER
Figure 2: Block Diagram
Table 2: Pin Descriptions
Pin
Type
Name
Description
1
AI
XIN
VCXO feedback
2
P
VDD
Power supply (+3.3V)
3
AI
XTUNE
VCXO tune
4
P
VSS
Ground
5
DO
CLK
Clock output
6
-
VDD
Power supply (+3.3V)
7
DO
VSS
Ground
8
AO
XOUT
VCXO drive
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input With Internal Pull-Up; DI
D = Input With Internal Pull-Down; DIO = Digital
Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low Pin
3.0 Functional Block Diagram
3.1 Voltage-Controlled Crystal Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6128 system components. Loading capacitance for
the crystal is internal to the FS6128. No external components (other than the resonator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The value of this voltage
controls the effective capacitance presented to the crystal. The actual amount that this load capacitance change will alter the oscillator
frequency depends on the characteristics of the crystal as well as the oscillator circuit itself.
It is important that the crystal load capacitance is specified correctly to “center” the tuning range. See Table 5.
A simple formula to obtain the “pulling” capability of a crystal oscillator is:
where:
C0 = the shunt (or holder) capacitance of the crystal
C1 = the motional capacitance of the crystal
CL1 and CL2 = the two extremes (minimum and maximum) of the applied load capacitance presented by the FS6128
Rev. 2 | Page 2 of 6 | www.onsemi.com
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