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參數(shù)資料
| 型號(hào)： | FS6128-07-XTP |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN W/VXCO 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類(lèi)型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 27MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
2008 SCILLC. All rights reserved.
Publication Order Number:
May 2008 – Rev. 2
FS6128-07/D
FS6128-07
PLL Clock Generator IC with VXCO
1.0 Key Features
Matches MK3727 center frequency characteristics
Phase-locked loop (PLL) device synthesizes output clock frequency from crystal oscillator or external reference clock
On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning
3.3V supply voltage
Very low phase noise PLL
Use with “pullable” 14pF crystals – no external pad-ding capacitors required
Small circuit board footprint (8-pin 0.150” SOIC)
Custom frequency selections available - contact your local ON Semiconductor sales representative for more information
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems.
At the core of the FS6128 is circuitry that implements a voltage-controlled crystal oscillator (VCXO) when an external resonator
(nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency
matching requirements, such as digital satellite receivers.
A high-resolution phase-locked loop generates an output clock (CLK) through a post-divider. The CLK frequency is ratiometrically
derived from the VCXO frequency. The locking of the CLK frequency to other system reference frequencies can eliminate unpredictable
artifacts in video systems and reduce electromagnetic interference (EMI) due to frequency harmonic stacking.
1
8
2
3
4
7
6
5
XIN
VDD
XTUNE
VSS
VDD
CLK
XOUT
FS
6128-
07
Figure 1: Pin Configuration – 8-pin (0.150”) SOIC
Table 1: Crystal / Output Frequencies
Device
fXIN (MHz)
CLK (MHz)
FS128-07
13.500
27.000
Note: Contact ON Semiconductor for custom PLL frequencies.
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| FS6131-01G-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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