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參數(shù)資料
| 型號： | FS6128-04G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL W/VCXO 8SOIC |
| 標準包裝： | 3,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 27MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
FS6128-04
A simple formula to obtain the “pulling” capability of a crystal oscillator is:
where:
C0 = the shunt (or holder) capacitance of the crystal
C1 = the motional capacitance of the crystal
CL1 and CL2 = the two extremes (minimum and maximum) of the applied load capacitance presented by the FS6128.
EXAMPLE: A crystal with the following parameters is used: C1 = 0.025pF and C0 = 6pF. Using the minimum and maximum
CL1 = 10pF, and CL2 = 20pF, the tuning range (peak-to-peak) is:
3.2 Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase locked loop architecture. The PLL multiplies the reference oscillator frequency to
the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise
specified).
4.0 Electrical Specifications
Table 3: Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Supply voltage (Vss = ground)
VDD
VSS – 0.5
7
V
Input voltage, DC
VI
VSS – 0.5
VDD + 0.5
V
Output voltage, DC
VO
VSS – 0.5
VDD + 0.5
V
Input clamp current, DC (VI < 0 or VI > VDD)
IIK
-50
50
mA
Output clamp current, DC (VI < 0 or VI > VDD)
IOK
-50
50
mA
Storage temperature range (non-condensing)
TS
-65
150
°C
Ambient temperature range, under bias
TA
-55
125
°C
Junction temperature
TJ
125
°C
Re-flow solder profile
Per IPC/JEDEC J-STD-020B
Input static discharge voltage protection (MLD-STD 883E, Method 3015.7)
2
kv
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress
rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied.
Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high energy
electrostatic discharge.
Table 4: Operating Conditions
Parameter
Symbol
Conditions/Descriptions
Min.
Typ.
Max.
Units
Supply voltage
VDD
3.3V ± 10%
3.0
3.3
3.6
V
Ambient operating temperature range
TA
0
70
°C
Crystal resonator frequency
fXTAL
Functional mode
12
13.5
18
MHz
Rev. 2 | Page 3 of 6 | www.onsemi.com
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| FS6128-05 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLL CLOCK GENERATOR IC WITH VCXO |
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| FS6128-07-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO CLOCK 27MHZ OUTPUT RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6128-07-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO CLOCK 27MHZ RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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