
FM8P54/56
Rev1.21 May 31, 2005
P.5/FM8P54/56
FEELING
TECHNOLOGY
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
TABLE 1.1: Registers File Map for FM8P54/56 Series
Address
Description
00h
INDF
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
07h
General Purpose Register
08h
PCON
09h
WUCON
0Ah
PCHBUF
0Bh
PDCON
0Ch
ODCON
0Dh
PHCON
0Eh
INTEN
0Fh
INTFLAG
10h ~ 3Fh
General Purpose Registers
TABLE 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
Name
B7
B6
B5
N/A (w)
OPTION
-
INTEDG
T0CS
05h (w)
IOSTA
Port A I/O Control Register
06h (w)
IOSTB
Port B I/O Control Register
TABLE 1.3: Operational Registers Map
Address
Name
B7
B6
B5
00h (r/w)
INDF
Uses contents of FSR to address data memory (not a physical register)
01h (r/w)
TMR0
8-bit real-time clock/counter
02h (r/w)
PCL
03h (r/w)
STATUS
GP2
GP1
GP0
04h (r/w)
FSR
*
*
05h (r/w)
PORTA
-
-
-
06h (r/w)
PORTB
IOB7
IOB6
IOB5
07h (r/w)
SRAM
General Purpose Registers
08h (r/w)
PCON
WDTE
EIS
LVDTE
09h (r/w)
WUCON
WUB7
WUB6
WUB5
0Ah (r/w)
PCHBUF
(1)
-
-
-
0Bh (r/w)
PDCON
/PDB3
/PDB2
/PDB1
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
0Eh (r/w)
INTEN
GIE
-
-
0Fh (r/w)
INTFLAG
-
-
-
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’
Note 1 : There is only 1 bit in FM8P54/54E. And there are 2 bits in FM8P56/56E.
N/A
OPTION
IOSTA
IOSTB
05h
06h
B4
T0SE
B3
PSA
B2
PS2
B1
PS1
B0
PS0
B4
B3
B2
B1
B0
Low order 8 bits of PC
TO
Indirect data memory address pointer
-
IOA3
IOB4
IOB3
PD
Z
DC
C
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
ROC
WUB4
-
/PDB0
ODB4
/PHB4
-
-
-
-
-
-
WUB3
-
/PDA3
ODB3
/PHB3
-
-
WUB2
/PDA2
ODB2
/PHB2
INTIE
INTIF
WUB1
2 MSBs Buffer of PC
/PDA1
ODB1
/PHB1
PBIE
PBIF
WUB0
/PDA0
ODB0
/PHB0
T0IE
T0IF