參數(shù)資料
型號(hào)： FM8P54
廠商： Electronic Theatre Controls, Inc.
英文描述： EPROM/ROM-Based 8-Bit Microcontroller Series
中文描述： 存儲(chǔ)器/基于ROM的8位微控制器系列
文件頁(yè)數(shù)： 34/50頁(yè)
文件大?。?/td> 368K
代理商： FM8P54
FM8P54/56
Rev1.21 May 31, 2005
P.34/FM8P54/56
FEELING
TECHNOLOGY
SLEEP
Syntax:
Operands:
Operation:
Enter SLEEP Mode
SLEEP
None
00h
WDT;
00h
WDT prescaler;
TO
1
;
PD
0
PD
TO
,
Time-out status bit (
prescaler are cleared.
The processor is put into SLEEP mode.
1
Status Affected:
Description:
PD
TO
) is set. The power-down status bit (
) is cleared. The WDT and its
Cycles:
SBCAR
Syntax:
Operands:
Subtract ACC from R with Carry
SBCAR R, d
0
≤
R
≤
63
d
∈
[0,1]
R + ACC + C
dest
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Operation:
Status Affected:
Description:
Cycles:
SUBAR
Syntax:
Operands:
Subtract ACC from R
SUBAR R, d
0
≤
R
≤
63
d
∈
[0,1]
R - ACC
dest
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Operation:
Status Affected:
Description:
Cycles:
SUBIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Subtract ACC from Immediate
SUBIA I
0
≤
I
255
≤
I - ACC
ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
SWAPR
Syntax:
Operands:
Swap nibbles in R
SWAPR R, d
0
≤
R
≤
63
d
∈
[0,1]
R<3:0>
dest<7:4>;
R<7:4>
dest<3:0>
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Operation:
Status Affected:
Description:
Cycles:
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