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參數(shù)資料
| 型號： | FM75M8 |
| 英文描述： | DIGITAL THERMOMETER|CMOS|SOP|8PIN |
| 中文描述： | 數(shù)字溫度計|的CMOS |?？苵 8引腳 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 2067K |
| 代理商： | FM75M8 |
9
F
www.fairchildsemi.com
FM75 Rev. A.4
Serial Data Bus Operation
General Operation
Writing to and reading from the FM75 registers is accomplished
via the SMBus-compatible two-wire serial interface. SMBus pro-
tocol requires that one device on the bus initiates and controls all
read and write operations. This device is called the
“
master
”
device. The master device also generates the SCL signal which is
the clock signal for all other devices on the bus. All other devices
on the bus are called
“
slave
”
devices. The FM75 is a slave device.
Both the master and slave devices can send and receive data on
the bus.
During SMBus operations, one data bit is transmitted per clock
cycle. All SMBus operations follow a repeating nine clock-cycle
pattern that consists of eight bits (one byte) of transmitted data
followed by an acknowledge (ACK) or not acknowledge (NACK)
from the receiving device. Note that there are no unused clock
cycles during any operation
—
therefore there must be no breaks
in the stream of data and ACKs/NACKs during data transfers.
Conversely having too few clock cycles can lead to incorrect
operation if an inadverstne 8-bit read from a 16-bit register occurs.
For most operations, SMBus protocol requires the SDA line to
remain stable (unmoving) whenever SCL is high
—
i.e., transitions
on the SDA line can only occur when SCL is low. The exceptions
to this rule are when the master device issues a start or stop signal.
Note that the slave device cannot issue a start or stop condition.
The following are definitions for some general SMBus terms:
Start Condition:
This condition occurs when the SDA line transi-
tions from high to low while SCL is high. The master device uses
this condition to indicate that a data transfer is about to begin.
Stop Condition:
This condition occurs when the SDA line transi-
tions from low to high while SCL is high. The master device uses
this condition to signal the end of a data transfer.
Acknowledge
and
Not Acknowledge:
When data is transferred
to the slave device it sends an acknowledge (ACK) after receiving
every byte of data. A master device sends an acknowledge (ACK)
following only the first byte read from a 2-byte register. The
receiving device sends an ACK by pulling SDA low for one clock.
Following the last byte, a master device sends a
“
not acknowl-
edge
”
(NACK) followed by a stop condition. A NACK is indicated
by leaving SDA high during the clock after the last byte.
Slave Address
Each slave device on the bus has a unique 7-bit address so the
master can identify which device is being read from or written to.
The FM75 address is as follows:
The four MSBs of the FM75 address are hardwired to 1001. The
three LSBs are user configurable by tying the A0, A1 and A2 pins
to either V
or ground. This provides eight different FM75
addresses, which allows up to eight FM75s to be connected to the
same bus.
Writing To and Reading From the FM75
All read and write operations must begin with a start signal
generated by the master device. After the start condition, the
master device must immediately send a slave address (7 bits)
followed by a read/write bit. If the slave address matches the
address of the FM75, the FM75 sends an ACK after receiving the
read/write bit by pulling the SDA line low for one clock. See Figure
8
–
Figure 13 for timing diagrams for all FM75 operations.
Setting the Pointer
For all operations the pointer stored in the Command Register
must be pointing to the register (Temperature, Configuration, T
OS
or T
) that is going to be written to or read from. To change the
pointer value in the Command Register, the read/write bit follow-
ing the address must be 0. This indicates that the master will now
write new information into the Command Register.
After the FM75 sends an ACK in response to receiving the address
and read/write bit, the master device must transmit an appropriate
8-bit pointer value as explained in the
Registers
section of this
data sheet. The FM75 will send an ACK after receiving the new
pointer data.
The pointer set operation is illustrated in Figure 8. Anytime a
pointer set is performed, it must be immediately followed by a read
or write operation. Note that the 6 MSBs of the pointer value must
be zero. If the 6 MSBs are not zero, the FM75 will not send an ACK
and will internally terminate the operation. Also recall that the
Command Register retains the current pointer value between
operations. Therefore, once a register is being pointed to, subse-
quent read operations do not require a pointer set cycle. Write
operations always require the pointer be reset.
1
0
0
1
A1
A2
A0
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