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參數(shù)資料
| 型號： | FM75M8 |
| 英文描述： | DIGITAL THERMOMETER|CMOS|SOP|8PIN |
| 中文描述： | 數(shù)字溫度計|的CMOS |?？苵 8引腳 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 2067K |
| 代理商： | FM75M8 |
4
F
www.fairchildsemi.com
FM75 Rev. A.4
Basic Operation
The FM75 temperature sensing circuitry continuously produces
an analog voltage that is proporational to the device temperature.
At regular intervals the FM75 converts the analog voltage to a
two
’
s complement digital value, which is placed into the tempera-
ture register.
The FM75 has an SMBus compatible digital serial interface which
allows the user to access the data in the temperature register at
any time. In addition, the serial interface gives the user easy
access to all other FM75 registers to customize operation of the
device.
The FM75 temperature-to-digital conversion can have 9, 10, 11,
or 12-bit resolution as selected by the user, providing 0.5
°
C,
0.25
°
C, 0.125
°
C, and 0.0625
°
C temperature resolution, respec-
tively. At power-up the default conversion resolution is 9-bits. The
conversion resolution is controlled by the R0 and R1 bits in the
Configuration Register.
Table 1 gives examples of the relationship between the output
digital data and the external temperature. The 9-bit, 10-bit, 11-bit
and 12-bit columns in Table
1 indicate the right-most bit in the
output data stream that can contain temperature information for
each conversion accuracy. Since the output digital data is in two
’
s-
complement format, the most significant bit of the temperature is
the
“
sign
”
bit. If the sign bit is a zero, the temperature is positive and
if the sign bit is a one, the temperature is negative.
The FM75 has a Shutdown Mode that reduces the operating
current of the FM75 to 150nA. This mode is controlled by the SD
bit in the configuration register.
Power Up Default Conditions
The FM75 always powers up in the following default state:
I
Thermostat mode: Comparator Mode
I
O.S. polarity: active low
I
Fault tolerance: 1 fault (i.e., F0 = 0 and F1 = 0 in the
Configuration Register)
I
T
OS
= 80
°
C
I
T
HYST
= 75
°
C
I
Register pointer: 00 (Temperature Register)
I
Conversion resolution: 9 bits (i.e., R0 = 0 and R1 = 0 in the
Configuration Register)
After power up these conditions can be reprogrammed via the
serial interface. Refer to the
Serial Data Bus Operation
section
for FM75 programming instructions.
Thermal Alarm Function
The FM75 thermal alarm function provides user programmable
thermostat capability and allows the FM75 to function as a stand
alone thermostat without using the serial interface. The Over-Limit
Signal (O.S.) output is the alarm output. This signal is an open
drain output, and at power-up this pin is configured with active-low
polarity.
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-
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-
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0
0
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0
0
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o
s
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-
1
0
0
0
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0
0
n
o
s
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R
t
-
0
0
0
0
0
0
0
C
°
5
2
1
+
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
C
°
5
2
6
0
0
1
+
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
C
°
5
2
1
5
+
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
C
°
5
2
1
+
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
C
°
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
°
5
2
1
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
C
°
5
2
3
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
C
°
5
2
6
0
4
1
1
0
1
0
1
0
0
1
1
1
1
0
0
0
0
C
°
5
5
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
Table 1. Relationship Between Temperature
and Digital Output
The O.S. polarity is controlled by the POL bit in the Configuration
Register. The user-programmable upper trip-point temperature
for the thermal alarm is stored in the T
OS
Register, and the user-
programmable hysteresis temperature (i.e., the lower trip point) is
stored in the T
HYST
Register.
The thermal alarm has two modes of operation: Comparator Mode
and Interrupt Mode. At power-up the default is Comparator Mode.
The alarm mode is controlled by the CMP/INTR bit in the Configu-
ration Register.
Fault Tolerance
In both modes the alarm
“
fault tolerance
”
setting plays a role in
determining when the O.S. output will be activated. Fault toler-
ance refers to the number of consecutive times an error condition
must be detected before the user is notified. Higher fault tolerance
settings can help eliminate false alarms caused by noise in the
system. The alarm fault tolerance is controlled by bits F0 and F1
in the Configuration Register. These bits can be used to set the
fault tolerance to 1, 2, 4 or 6 as shown in Table 4. At power-up,
these bits both default to 0 (fault tolerance = 1).
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