參數(shù)資料
型號(hào)： FM32256-G
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Integrated Processor Companion with Memory
中文描述： 綜合處理器與記憶體伴侶
文件頁(yè)數(shù)： 14/20頁(yè)
文件大小： 285K
代理商： FM32256-G
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM32xx acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a 1. The
operation is now a read from the current address.
Read operations are illustrated below.
FM3204/16/64/256
Rev 2.1
Dec. 2004
Page 14 of 20
Companion Write Operation
All Companion writes operate in a similar manner to
memory writes. The distinction is that a different
device ID is used and only one byte of address is
needed instead of two. Figure 15 illustrates a single
byte write to this device.
Companion Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM32xx will begin shifting data out from the current
register address on the next clock. Auto-increment
operates for the special function registers as with the
memory address. A current address read for the
registers look exactly like the memory except that the
device ID is different.
The FM32xx contains two separate address registers,
one for the memory address and the other for the
register address. This allows the contents of one
address register to be modified without affecting the
current address of the other register. For example,
this would allow an interrupted read to the memory
while still providing fast access to a companion
register. A subsequent memory read will then
continue from the memory address where it
previously left off, without requiring the load of a
new memory address. However, a write sequence
always requires an address to be supplied.
Figure 12. Current Address Memory Read
Figure 13. Sequential Memory Read
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM32xx
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM32xx
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Data Byte
A
Acknowledge
相關(guān)PDF資料
PDF描述
FM32256-S Integrated Processor Companion with Memory
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FM3264-S Integrated Processor Companion with Memory
FM34W02ULZ RoHS Compliant:Yes RoHS Compliant: Yes
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FM32256-S 功能描述:監(jiān)控電路 256K w/Pwr Mon WDT Bat Sw Pwr Fail RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類(lèi)型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
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