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參數(shù)資料
| 型號： | FM18L08-70-S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 80K |
| 代理商： | FM18L08-70-S |
Ramtron
FM18L08
23 March 2001
3/11
Overview
The FM18L08 is a bytewide FRAM logically
organized as 32,768 x 8. It is accessed using an
industry standard parallel interface. The FM18L08 is
inherently nonvolatile via its unique ferroelectric
process. All data written to the part is immediately
nonvolatile with no delay. Functional operation of the
FRAM memory is similar to SRAM type devices. The
major operating difference between the FM18L08 and
an SRAM (besides nonvolatile storage) is that the
FM18L08 latches the address on the falling edge of
/CE.
Memory Operation
Users access 32,768 memory locations each with 8
data bits through a parallel interface. The access and
cycle time are the same for read and write memory
operations. Writes occur immediately at the end of the
access with no delay. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. A pre-charge
operation, where /CE goes inactive, is a part of every
memory cycle. Thus unlike SRAM, the access and
cycle times are not equal.
Note that the FM18L08 contains a limited low voltage
write protection circuit. This will prevent access when
VDD is much lower than the specified operating
range. It is still the user’s responsibility to ensure that
VDD is within data sheet tolerances to prevent
incorrect operation.
The FM18L08 is designed to operate in a manner very
similar to other bytewide memory products. For users
familiar with SRAM, the performance is comparable
but the bytewide interface operates in a slightly
different manner as described below. For users
familiar with EEPROM, the obvious differences result
from the higher write performance of FRAM
technology including NoDelay writes and from
unlimited write endurance.
Read Operation
A read operation begins on the falling edge of /CE. At
this time, the address bits are latched and a memory
cycle is initiated. Once started, a full memory cycle
must be completed internally regardless of the state of
/CE. Data becomes available on the bus after the
access time has been satisfied.
After the address has been latched, the address value
may be changed upon satisfying the hold time
parameter. Unlike an SRAM, changing address values
will have no effect on the memory operation after the
address is latched.
The FM18L08 will drive the data bus when /OE is
asserted to a low state. If /OE is asserted after the
memory access time has been satisfied, the data bus
will be driven with valid data. If /OE is asserted prior
to completion of the memory access, the data bus will
be driven when valid data is available. This feature
minimizes supply current in the system by eliminating
transients due to invalid data. When /OE is inactive
the data bus will remain tri-stated.
Write Operation
Writes operations require the same time as reads. The
FM18L08 supports both /CE- and /WE-controlled
write cycles. In all cases, the address is latched on the
falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM18L08 will not drive
the data bus regardless of the state of /OE.
In a /WE-controlled write, the memory cycle begins
on the falling edge of /CE. The /WE signal falls after
the falling edge of /CE. Therefore, the memory cycle
begins as a read. The data bus will be driven
according to the state of /OE until /WE falls. The
timing of both /CE- and /WE-controlled write cycles is
shown in the electrical specifications.
Write access to the array begins asynchronously
after the memory cycle is initiated. The write access
terminates on the rising edge of /WE or /CE,
whichever is first. Data set-up time, as shown in the
electrical specifications, indicates the interval during
which data cannot change prior to the end of the write
access.
Unlike other truly nonvolatile memory technologies,
there is no write delay with FRAM. Since the read and
write access times of the underlying memory are the
same, the user experiences no delay through the bus.
The entire memory operation occurs in a single bus
cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling,
a technique used with EEPROMs to determine if a
write is complete, is unnecessary.
Pre-charge Operation
The pre-charge operation is an internal condition
where the state of the memory is prepared for a new
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM18L08-70-SG | 功能描述:F-RAM 256K (32Kx8) 70ns 3V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM18L08-70-SG | 制造商:Ramtron International Corporation 功能描述:Nonvolatile SRAM Memory IC Memory Type:F |
| FM18L08-70-SGTR | 功能描述:F-RAM 256K (32Kx8) 70ns 3V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM18L08-70-STR | 功能描述:F-RAM 256K (32Kx8) 70ns 3V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM18L08-70-TG | 功能描述:F-RAM 256K (32Kx8) 70ns 3V RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
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