參數(shù)資料
型號(hào): FM18L08-70-P
廠商: Electronic Theatre Controls, Inc.
英文描述: .050 X .050 MICRO STRIPS
中文描述: 256Kb的2.7 - 3.6V的Bytewide FRAM存儲(chǔ)器
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 80K
代理商: FM18L08-70-P
Ramtron
FM18L08
23 March 2001
2/11
Figure 1. Block Diagram
Address
Latch
A0-A14
CE
Control
Logic
WE
Row
Decoder
Block Decoder
Column Decoder
A0-A7
A8-A9
A10-A14
I/O Latch
Bus Driver
OE
32,768 x 8 FRAM Array
DQ0-7
Pin Description
Pin Name
A0-A14
Pin Number
1-10, 21, 23-26
I/O
I
Pin Description
Address. The 15 address lines select one of 32,768 bytes in the FRAM
array. The address value will be latched on the falling edge of /CE.
Data. 8-bit bi-directional data bus for accessing the FRAM array.
Chip Enable. /CE selects the device when low. The falling edge of /CE
causes the address to be latched internally. Address changes that
occur after /CE goes low will be ignored until the next falling edge
occurs.
Output Enable. When /OE is low the FM18L08 drives the data bus
when valid data is available. Taking /OE high causes the DQ pins to be
tri-stated.
Write Enable. Taking /WE low causes the FM18L08 to write the
contents of the data bus to the address location latched by the falling
edge of /CE.
Supply Voltage.
Ground.
DQ0-7
/CE
11-13, 15-19
20
I/O
I
/OE
22
I
/WE
27
I
VDD
VSS
28
14
I
I
Functional Truth Table
/CE
H
L
L
/WE
X
X
H
L
/OE
X
X
L
X
Function
Standby/Precharge
Latch Address
Read
Write
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