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參數(shù)資料
| 型號： | FIR Filters |
| 廠商： | Altera Corporation |
| 英文描述： | FIR Compiler(有限的脈沖響應(yīng)濾波器) |
| 中文描述： | 飛行編譯器（有限的脈沖響應(yīng)濾波器） |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 323K |
| 代理商： | FIR FILTERS |
2
Altera Corporation
FS 1: FIR Filters
Adding more taps to the filter does not significantly change the
speed for any given precision width. See
Figure 1
.
Figure 1. Speed for 8-Bit Input Filters in FLEX 8000A Devices
Altera’s FIR filters provide the designer with a great deal of
flexibility because they can be customized for specialized
applications by modifying the source code. In addition, the filters’
flexibility allows designers to implement decimating or
interpolating filters, and to use the vector multiplier from these
reference designs to implement any operation that has multiply and
accumulate (MACs) functions, where one set of multiplicands is
constant.
All linear-phase FIR filters have symmetric coefficients; therefore,
the designer can take advantage of this symmetry by adding taps
prior to multiplication. For example, an 8-tap FIR filter can be
implemented with a 4-input vector multiplier. The vector multiplier
performs the following multiplication:
+ (
h
(3)
×
s
(3)) + (
h
(4)
×
s
(4)), where
are pre-added data samples. The coefficients must be fixed prior to
compilation, although you can change the coefficients by
reconfiguring the device. Thus, it is possible to change the filter
function in response to user controls. The device can be reconfigured
in less than 100 ms. To be implemented in FLEX devices, all FIR
filters require MAX+PLUS II version 6.0 or higher.
y
= (
h
(1)
×
s
(1)) + (
h
(2)
×
s
(2))
s
(
n
h
(
n
) are FIR coefficients, and
)
f
See
Application Note 73
(
Implementing FIR Filters in FLEX Devices
)
for
a complete description of vector multipliers and the FIR filter
architecture.
0
0
Speed (MSPS)
8
16
24
32
20
40
60
80
100
120
64
Taps
Serial Filters
Parallel Filters
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