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參數(shù)資料
| 型號： | FIR Filters |
| 廠商： | Altera Corporation |
| 英文描述： | FIR Compiler(有限的脈沖響應濾波器) |
| 中文描述： | 飛行編譯器（有限的脈沖響應濾波器） |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 323K |
| 代理商： | FIR FILTERS |
Altera Corporation
12
fir_16ts & fir_64ts
Serial FIR Filters
Features
I
I
I
I
I
Serial FIR filter reference designs
Serial implementation for minimum resource usage
High performance: > 6 MSPS
Parameterized data widths, pipelining, and symmetry
Symmetrical or antisymmetrical coefficients
General
Description
The Altera serial FIR filters are small, linear-phase designs with operation
speeds of over 6 MSPS. By efficiently using the Altera FLEX architecture,
these filters provide extremely fast, flexible, and cost-effective design
solutions. In addition, the filters use bit-serial computation, making them
significantly smaller than parallel implementations. The filters are
implemented using the vector-multiplier approach described in
Application Note 73
(
Implementing FIR Filters in FLEX Devices
)
. The
coefficients are stored in LUTs and their values are determined at
compilation; however, the coefficients can be changed by reconfiguring
the device. Other tap lengths are available by modifying a copy of the
AHDL TDF. These designs convert parallel data input into serial internal
data for processing. Thus, each input sample must be applied to the input
(
xin)
for
width
+
1
clock cycles.
Figure 10
shows the symbol for the 16-tap serial FIR filter. All other serial
FIR filters in the Altera DSP Design Kit have the same symbol.
Coefficients are defined in an Include File (
.inc
) called
coef.inc
.
Figure 10. Serial FIR Filter Symbol
FIR_16TS
Y[OUTPUT_P..1]
ROM_P =
OUTPUT_P =
CLK
ACLR
XIN[WIDTH..1]
PIPELINED =
SYM =
WIDTH =
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