參數(shù)資料
型號: FIN3383MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 2MM TERMINAL STRIPS
中文描述: QUAD LINE DRIVER, PDSO56
封裝: 6.10 MM, MO-153, TSSOP-56
文件頁數(shù): 7/9頁
文件大小: 281K
代理商: FIN3383MTD
7
www.fairchildsemi.com
F
AC Loading and Waveforms
(Continued)
FIGURE 9. Transmitter Output Pulse Bit Position
Note:
This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter
±
3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left
3ns and to the right
+
3ns when data is HIGH.
The
±
3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross V
CC
range with 100mV noise
(V
CC
noise frequency
<
2 MHz).
FIGURE 10. Timing Diagram of Transmitter Clock Input with Jitter
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