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參數(shù)資料
| 型號： | FIN324CMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 0K |
| 描述： | IC SER DES 24BIT ULP 40-MLP |
| 產(chǎn)品變化通告： | Design/Process Change 07/May/2007 |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | FIN324CMLXDKR |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.1.4
10
SerDes
FIN324C
—
24-Bit
Ultra-Low
Power
Serializer
/
Deserializer
Supporting
Single
and
Dual
Displays
Application Diagrams (Continued)
VDDP1
A4
B4
D4:G6
C4
C3
A3
B3
A2 NC
B2
NC
A1
D3
F3
G3
G2
B1
Notes:
1.
Dual display R/W Intel interface.
2.
3.
4.
5.
Unused slave output pin must be NC (No Connection).
GPIO signal used to select READ or WRITE functionality. Connected to CKSEL and R/W.
Displays selected via the chip selects.
Pin numbers for BGA package.
.
/RE
/WE
GPIO
/STBY
/RES
CKSEL0
CKSEL1
Main Display
/RE
/WE
DATA[17:0]
ADDR
/CS1
Sub-Display
/RE
/WE
DATA[7:0]
ADDR
/CS0
Edge Rate Control Option
SLEW must be connected
to VDDP or GND for low
power.
VDDP VDDS/A
STRB0
STRB1
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
DATA[17:0]
DP[17:0]
CNTL[0]
CNTL[1]
ADDR
/CS0
/CS1
CNTL[3]
CNTL[2]
CNTL[4]
VDDP VDDS/A
WCLK0
WCLK1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
SLEW
/RES
VDDP
VDDP1
VDDS/A
VDDP2
VDDS/A
CKS+
CKS-
DS+
DS-
CKS+
CKS-
DS+
DS-
D1
E1
G1
F1
E3
D2
C1
G1
F1
D1
E1
E3
D2
C1
A4
B4
D4:G6
C4
C3
A3
B3
A2
B2
A1
D3
F3
G3
G2
B1
C2
E2
F2
C2
E2
F2
Module 1
VDDP2
Baseband
Processor
Master
Slave
GND
Figure 10.
Dual R/W x86-Style Microcontroller Display Interface
Additional Application Information
Flex Cabling:
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this
serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
Keep all four differential Serial Wires the same length.
Do not allow noisy signals over or near differential serial wires.
Example: No CMOS traces over differential serial wires.
Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
Design goal of 100-ohms differential characteristic impedance.
Do not place test points on differential serial wires.
Use differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales rep, or
contact Fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
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| FIN3383MTDX | 功能描述:LVDS 接口集成電路 Link Serializer LV 28Bit RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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