參數(shù)資料
型號： FIN324CMLX
廠商： Fairchild Semiconductor
文件頁數(shù)： 15/19頁
文件大?。?/td> 0K
描述： IC SER DES 24BIT ULP 40-MLP
產(chǎn)品變化通告： Design/Process Change 07/May/2007
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FIN324CMLXDKR
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.1.4
5
SerDes
FIN324C
—
24-Bit
Ultra-Low
Power
Serializer
/
Deserializer
Supporting
Single
and
Dual
Displays
System Control Pins
(M/S) Master / Slave Selection:
A given device can be
configured as a master or slave device based on the
state of the M/S pin.
Table 1. Master/Slave
M/S
Configuration
0
Slave Mode
1
Master Mode
(PAR/SPI) SPI Mode Selection:
The PAR/SPI signal
configures STRB0(WCLK0) for SPI mode write operation.
STRB1(WCLK1) always operates in parallel mode.
Control signals CNTL[5:0] all pass in SPI mode. In SPI
mode, the SCLK signal is used to strobe the serializer.
SPI mode supports SPI writes only.
Table 2. Channel 0 PAR/SPI Configuration
PAR
/SPI
M/S=1 MASTER
M/S=0 SLAVE
0
SPI Mode
SDAT=CNTL[4]
SCLK=CNTL[5]
/CS=STRB0
SPI Mode
SDAT=DP[7] & CNTL[4]
SCLK=DP[6] & CNTL[5]
/CS=WCLK0
1
Parallel Mode
(CKSEL) Strobe Selection Signal:
The CKSEL signal
exists only on the master device and determines which
strobe signal is active. The active strobe signal is
selected by CKSEL and PAR/SPI inputs.
Table 3. PAR/SPI
PAR
/SPI
CKSEL
Master
Strobe
Source
Slave Strobe
Source
0
CNTL[5]
DP[6] & CNTL[5]
0
1
STRB1
WCLK1
1
0
STRB0
WCLK0
1
STRB1
WCLK1
(/RES, /STBY) Reset and Standby Mode Functionality:
Reset and standby mode functionality is determined by
the state of the /RES and /STBY signals for the master
device and the /RES and internal standby-detect signal
for the slave device. The /RES control signal has a filter
that rejects spurious pulses on /RES.
Table 4. Reset and Standby Modes
/RES
/STBY
(2)
Master
Slave
0
X
Reset Mode
1
0
Standby
Mode
Standby
Mode
(2)
1
Operating
Mode
Operating
Mode
Note:
2.
The slave device is put into standby mode through
control signals sent from the master device.
Table 5. Reset and Standby Mode States
Pin
Master
Reset / Standby
Slave
Reset
Slave
Standby
DP[17:0]
Disabled
Low
Last Data
CNTL[5:0]
Disabled
Low
Last Data
STRB[0:1]
(WCLK[0:1])
Disabled
High
(SLEW) Slew Control:
The slew control operates only
when in slave mode. This signal changes the edge rate
of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0
signals to optimize edge rate for the load being driven.
Master read mode outputs have “slow” edge rates. See
the AC Deserializer Specifications table for “slow” and
“fast” edge rates.
Table 6. Slew Rate Control
/STBY (SLEW)
Slave M/S=0
0
“Slow”
1
“Fast”
CMOS I/O Signals
System Control Signals
The system control signals consist of M/S, /RES,
/STBY(SLEW), PAR/SPI, and CKSEL. For connectivity
flexibility, these signals are over-voltage tolerant to the
maximum supply voltage connected to the device. This
allows these signals to be tied HIGH to either a VDDS or
VDDP supply without static current consumption. These
signals are all CMOS inputs and should never be
allowed to float.
Parallel I/O Signals
The parallel data port signals consist of the DP[17:0],
CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals.
These signals have built-in voltage translation, allowing
the signals of the master and slave to be connected to
different VDDP supply voltages.
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